- Cadence Design Systems, Inc. (San Jose, CA)
- …devices.Responsibilities include:* Technical presales of Memory IP* Gain expertise in memory controller and PHY IPs and DDR protocols* Work closely with ... - DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6* Perl/Python Scripts* Experience on memory subsystem verification and/or performance analysis* Strong...design* Knowledge of AXI, DFI protocols* Working knowledge of memory controller and memory PHY… more