- Cisco (San Jose, CA)
- …track manner Who You'll Work With You will be in the Silicon One development organization as an ASIC DFT Technical Program Manager in San Jose, CA with a ... the industry. What You'll Do * Work closely with DFT architecting leads to define and the DFT... DFT architecting leads to define and the DFT implementation specifications * Responsible for closely managing the… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer, DFT Responsibilities: 1. Develop and implement DFT strategies… more
- Micron Technology, Inc. (San Jose, CA)
- …and data/control flows for the controller and its component IPs. + ** Technical Guidance:** Define requirements for ASIC design, verification, physical ... and groundbreaking technology while rapidly growing your abilities. We are seeking an ** ASIC Architect** for Micron's ASIC architecture team. You should have… more
- Meta (Sunnyvale, CA)
- …generation models and design with insights from silicon characterization. 5. Leverage deep technical skill set in ASIC design, and/or complex test development to ... **Summary:** Meta is hiring ASIC Engineers within the Infrastructure organization. We are...silicon solutions - from early architecture and design inputs, dft concepts, bring-up and post-silicon characterization. 2. Create/develop characterization… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run Logic/Physical Synthesis using advanced… more
- Cisco (San Jose, CA)
- …Minimum Qualifications * Including but not limited to an upcoming graduate of a technical degree or certification program from a Technical Boot Camp, ... Power Integrity, and DFx. * Solid understanding of engineering fundamentals and technical problem-solving skills * Familiarity with ASIC design flow, including… more
- Cisco (San Jose, CA)
- …Minimum Qualifications * Including but not limited to a graduate/upcoming graduate of a technical degree or certification program from a Technical Boot Camp, ... you directly if a relevant position opens. Who You'll Work With The ASIC Group works closely with other development teams within Cisco, including marketing, system… more
- Amazon (Cupertino, CA)
- …to improve physical design flows and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications - Enrolled ... in a Bachelors' degree program or higher in Electrical Engineering, Computer Engineering, or...in Electrical Engineering or Computer Engineering - Previous relevant technical internship experience - Experience with FinFET design, Clock/Power… more
- Google (Mountain View, CA)
- Please complete your application before November 22nd, 2024. Participation in the internship program requires that you are located in the United States for the ... duration of the internship program . This internship is intended for students in their...in Electrical, Electronics, and Communication Engineering or a related technical field. Google is a global company and, in… more
- Google (Sunnyvale, CA)
- …degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience. + 10 years of experience ... data trends. + Knowledge of semiconductor device physics and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and full-chip static timing… more
- Qualcomm (Santa Clara, CA)
- …to push your limitless potential. Join us for our US 2025 summer intern program ! As a Qualcomm **Hardware Engineering Intern,** you'll have the opportunity to push ... (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design-for-Test ( DFT ), Physical Design (Place & route, CTS, timing closure),… more