- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
- Amazon (Cupertino, CA)
- …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity… more
- Amazon (Cupertino, CA)
- …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies ... in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis, place and route,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and … more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design … more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... floor-planning and back end teams to help craft the physical floorplan of the chip and explains the programming...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design … more
- Cisco (San Jose, CA)
- …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... the latest deep submicron silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability to manage multiple tasks and… more
- Google (Mountain View, CA)
- ASIC Lead Engineer , Project Taara (Fixed Term) Hardware Engineering Mountain View, CA This is a fixed-term contract position for 12 months About the team: At X ... About the Role: The Taara Project is seeking an ASIC lead engineer to drive the next...input from various teams, contribute to the detailed circuit design , own the foundry submission process, oversee physical… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/ Physical Synthesis using advanced ... in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with...Power, Performance, Area. 14. Knowledge of front-end and back-end ASIC tools. 15. Experience with RTL design … more
- NVIDIA (Santa Clara, CA)
- …performance designs + Expertise in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication skills + Background in ... We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking...Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our next-generation mobile,… more
- Cisco (San Jose, CA)
- …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... a relevant position opens. Who You'll Work With The ASIC Group works closely with other development teams within...silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability… more
- Amazon (Sunnyvale, CA)
- …in Electrical / Communications Engineering - 7+ years of experience in digital design - Experience with physical implementation flows Amazon is committed to ... Estimate power, performance, and area for significant IPs early in design cycle - Execute on design specifications to deliver high quality RTL - Ensure quality… more
- Amazon (Cupertino, CA)
- …as part of Amazon's machine learning custom silicon solutions * Work with physical design teams to achieve performance and area requirements. * Develop ... Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but...while also being deeply important to our customers. We design and build every component of our hardware and… more
- Cisco (San Jose, CA)
- …to physical design signoff activities. What You'll Do You will be part of ASIC physical design Team which is responsible for full Chip physical ... -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture...from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: * Perform full… more