- Meta (Sunnyvale, CA)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...13. 3+ Years of experience as a Front End Synthesis & Integration Engineer 14. Experience with… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...16. Experience with SOC Design Integration & Front End Implementation 17. Experience with Front End Synthesis … more
- Meta (Sunnyvale, CA)
- … ASIC engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Implementation Responsibilities: 1. Participate in ... **Summary:** Meta is seeking an ASIC Engineer Intern to join our...You will have an opportunity to participate in design implementation /emulation, physical design, EDA infrastructure methods, and design power… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...the DFT coverage for Stuck-at faults. 5. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate… more
- Broadcom (San Jose, CA)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC implementation engineer with demonstrated expertise in multiple ... Electrical Engineering or Computer Engineering and 8+ years of related ASIC implementation experience or Masters degree in Electrical Engineering or Computer… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS 4. Lint, CDC, Synthesis , & Power Optimization 5. Soft and hard IP… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to ... of ASIC design flow including RTL design, verification, logic synthesis , timing analysis, ECO, and post silicon debug. + Strong interpersonal skills… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS. 3. Lint, CDC, Synthesis , & Power Optimization. 4. Soft and hard IP… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... frequencies about 1 GHz + Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF...- TCL or Perl or Python + Experience in Synthesis and Formal is a plus + Excellent verbal… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... CPUs and GPUs. + Explore design space, create optimum floorplan, drive synthesis , physical implementation , and timing closure by understanding arch/logic as… more
- NVIDIA (Santa Clara, CA)
- …focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation . This ... We are now looking for a Logic Design Engineer . As a member of our CPU Logic...ASIC design flow including RTL design, verification, logic synthesis , prototyping, DFT, timing analysis, floor-planning, ECO, bring-up &… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... including clock domain crossing checks and MTBF analysis, logic synthesis , netlist quality checks, etc. + Help in all...timing constraints generation and management, and ECO generation and implementation . What we need to see: + BS (or… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 6. Collaboration with implementation team to close the design on timing and… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug. 5. Collaboration with implementation team to close the design on timing and… more
- Amazon (Sunnyvale, CA)
- …RTL - Ensure quality by running and tracking results of front-end tools including: Synthesis , Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon ... - 7+ years of experience in digital design - Experience with physical implementation flows Amazon is committed to a diverse and inclusive workplace. Amazon is… more
- NVIDIA (Santa Clara, CA)
- …most powerful design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams with advanced implementation ... NVIDIA's chip design methodology! We're responsible for the Front-End Design Implementation methodology for all of NVIDIA's semiconductor products. As part of… more
- Qualcomm (Santa Clara, CA)
- …through the full ASIC development process from specification, RTL implementation , verification, synthesis , timing closure, emulation and post silicon bring ... WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/ Implementation , power estimates and power reduction techniques. **Minimum Qualifications:**… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Semiconductor fundamentals and Static Timing Analysis is required + Prior experience with ASIC digital implementation flows and EDA tools is required; Experience ... in the field of artificial intelligence and machine learning. Lead Application Engineer is responsible for providing pre-sales and post-sales technical support for… more