- Google (Sunnyvale, CA)
- …sign-off for ASICs. Preferred qualifications: + 12 years of experience in the domain of physical design and static timing analysis. + Experience leading one ... equivalent practical experience. + 5 years of experience in static timing (ie, to create full chip timing constraints,...timing ECO creation). + Experience in working across various physical design areas (ie, EDA scripting, block… more
- SpaceX (Sunnyvale, CA)
- Principal SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... goal of enabling human life on Mars. PRINCIPAL SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical… more
- Google (Sunnyvale, CA)
- …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Physical Design Engineer on the chip implementation team, ... practical experience. + 2 years of experience in ASIC physical design and methodologies in advanced nodes....static timing, power and clock distribution, CDC, LEC, physical verification on blocks, sub systems, or full chip).… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated ASIC Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …years of experience. Master's degree preferred. + Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is ... an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support...+ Bachelor's degree with at least 3-6 years of design /EDA experience or Master's degree with at least 4… more
- NVIDIA (Santa Clara, CA)
- …(or equivalent experience) + 5+ years of experience in Physical design /Timing + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing ... constraints generation and management, and timing convergence + Expertise in physical design , optimization, and ECO implementation eg cell sizing, buffering, VT… more
- Microsoft Corporation (Mountain View, CA)
- …ensure proper for stuck-at and transition fault coverage is achieved. + Collaborate with Physical Design (PD) team to ensure proper DFT insertion and timing ... the Cloud infrastructure. We are looking for a **Senior Design for Test (DFT) Engineer ** to join...every two years thereafter._** **Preferred Qualifications:** + Experience with static timing tools and timing closure + Deep knowledge… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Principal** ** Design Engineer ** (Silicon) to join the team. Microsoft's mission is to ... the microarchitecture of IP blocks, Register Transfer Level (RTL) design , synthesis, static timing analysis, and silicon...Throughout the program you will be interacting with architecture, design , verification and physical design … more
- Teledyne (Mountain View, CA)
- …for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design ... of integrated circuits and related development. Participates in all phases of physical design , including floor planning, clock synthesis, timing optimization,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... analysis on the design . + Drive the design and physical implementation of digital and/or...Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for… more
- NVIDIA (Santa Clara, CA)
- …algorithms, computer architecture and computer science theory + Experienced with VLSI physical design and packaging + Flexibility/adaptability for working in a ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …block and Chip top level You will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R, and participating in silicon ... RTL design of high-speed interfaces. Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts. Knowledge of the… more
- Cadence Design Systems, Inc. (San Jose, CA)
- … static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly… more
- NVIDIA (Santa Clara, CA)
- …circuits for hardware security, adaptive clocking and power management solutions + Drive the design and physical implementation of custom digital IPs from RTL to ... impact on the world! What you'll be doing: + Participate in ground breaking Processor design in deep submicron technologies. + Work as part of a global circuits team… more
- Snap Inc. (Palo Alto, CA)
- …glasses that bring augmented reality to life. We're looking for a Finite Element Analysis Engineer to join the Snap Lab team at Snap Inc! What you'll do: + Perform ... static and dynamic structural simulations using Abaqus or Ansys...hardware. + Lead and coordinate with partner teams _(Product Design , Reliability, Quality, etc.)_ to validate the predictions of… more
- Siemens Digital Industries Software (Fremont, CA)
- …Engineering, or other related fields. + Minimum of 5 year's experience of design , static timing analysis, and Tcl/Python scripting + Software Engineering skills, ... + Knowledge and understanding of all aspects of a design flow - particularly SDC, static timing...creed, religion, national origin, citizenship status, ancestry, sex, age, physical or mental disability unrelated to ability, marital status,… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of ... Work hard. Have Fun. Make history. At Amazon, DFT ( Design -for-Testability) is a multi-faceted job that involves architecture definition,...patterns generation, chip bring-up and more. As a DFT Engineer , you will impact and see the device through… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction. + Good understanding of Cadence ... Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Solution product. Genus is a complete product that encompasses logic synthesis and physical design . The product breadth means we are looking for skilled ... to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on… more