• Sr . SOC / ASIC

    SpaceX (Sunnyvale, CA)
    Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL ...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year… more
    SpaceX (08/16/24)
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  • Sr . SOC Design Engineer - STA,…

    Amazon (Sunnyvale, CA)
    …Edge that is powering the latest generation of Echo devices is looking for a Sr . SOC Design Engineer-STA to continue to innovate on behalf of our customers. ... - Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. - Full chip timing constraints development, full chip / Sub-System STA and… more
    Amazon (09/17/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of ... SOC clocking. The team collaborates with the front end...floor-planning and back end teams to help craft the physical floorplan of the chip and explains the programming… more
    NVIDIA (08/09/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically...and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis,… more
    NVIDIA (08/07/24)
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  • Senior ASIC Design Engineer…

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU ... floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency… more
    NVIDIA (09/04/24)
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  • Senior SoC Technical Program…

    Amazon (Sunnyvale, CA)
    …complete the execution of projects in time. Key job responsibilities As a Senior SoC Technical Program Manager, you will interface with cross-functional ... you will interface with cross-functional engineering and program/product management teams to develop ASIC / SOC solutions that will go into Amazon Devices. In this… more
    Amazon (09/17/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    …computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip ( SOC ) group is looking for a top ASIC Engineer with a curiosity ... Are you looking for a SOC Design Engineer opportunity? If yes, come and...GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design, CAD, Package Design, Software,… more
    NVIDIA (08/09/24)
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  • Sr . DDR IP Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr . DDR IP Design Engineer (Silicon Engineering) at...cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing… more
    SpaceX (07/22/24)
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  • AE Senior Manager - Serdes Applications

    Cadence Design Systems, Inc. (San Jose, CA)
    …team of skilled engineers and working with customers to develop solutions for their System/ ASIC / SoC designs using the Cadence Serdes IP portfolio. This is a ... make an impact on the world of technology. Title: Sr . AE Manager - Serdes Applications Location: San Jose,...pre-sales role. It is perfect for someone who has System/ ASIC / SoC design experience and great interpersonal and… more
    Cadence Design Systems, Inc. (09/19/24)
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  • Engineering Director, Physical Design

    Google (Mountain View, CA)
    …networking technologies that power all of Google's services. Manage a COT and ASIC Physical design group primarily responsible for TPU development (DeepSea ... experience. + 15 years of experience in a Silicon Physical Design role. + 10 years of experience in...+ 20 years of PD experience in complex processor-class ASIC or SoC programs, including track record… more
    Google (09/28/24)
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  • Senior Silicon Engineering

    Microsoft Corporation (Santa Clara, CA)
    …key components of functional validation of complex Application-Specific Integrated Circuit ( ASIC ) System on Chip ( SOC ) using Universal Verification Methodology ... Azure Hardware Systems & Infrastructure group is seeking a ** Senior Silicon Engineer** . You will join our front-end...(UVM)/C test bench + Perform Pre-Silicon SoC verification, Post-Silicon/ Field-Programmable Gate Array (FPGA) validation by… more
    Microsoft Corporation (09/18/24)
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  • Senior Security Architect - Hardware

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Hardware Security Architect: NVIDIA is seeking an experienced hardware security architect interested in a chance to define, craft, ... 8+ years of meaningful relevant work or research experience. + Experience with the ASIC design process and architecture of large SoCs or GPUs. + Programming and… more
    NVIDIA (08/14/24)
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  • 3D IC Solutions Engineer- Package Design Engineer

    Siemens Digital Industries Software (Fremont, CA)
    …a plus. + Working knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... Route solutions: Siemens (Aprisa, Nitro, Tanner), Synopsys (IC/3DIC/Custom Compiler), Cadence ( SoC Encounter, Innovus, Virtuoso) o Physical Verification: DRC,… more
    Siemens Digital Industries Software (08/25/24)
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