- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep ... understanding of timing constraints, such as clock groups, various exceptions, clock... constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints,… more
- Cisco (San Jose, CA)
- …goals, and love to win as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding ... Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing ...and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools… more
- Cisco (San Jose, CA)
- …development - Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis * Past experience with Post silicon validation ... in San Jose, CA with a primary focus on Design-for- Test . You will work with Front-end RTL teams, backend...What You'll Do * Responsible for implementing the Hardware Design-for- Test (DFT) features that support ATE, in-system test… more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- Microsoft Corporation (Mountain View, CA)
- …a difference in the world. We are looking for a **Fabric IP Design Engineer ** to join the team. **Growth Mindset** We fundamentally believe that we need a ... The Cloud Compute Development Organization is seeking a **Fabric IP Design Engineer ** to join our IP development team covering micro-architecture implementation, RTL… more
- Qualcomm (Santa Clara, CA)
- …positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools ... responsibilities in this role involves good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning,… more
- Meta (Sunnyvale, CA)
- …and verification. 3. Define timing constraints, run synthesis and static timing analysis. 4. Support the test program development, chip validation and ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...including UPF flow. 19. Experience with design synthesis and timing optimization. 20. Master's degree in Computer Science, Computer… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + Contribute ... verification reviews + Cover digital backend design from synthesis, static timing and logic equivalent checking + Creating documentation targeting design,… more
- Meta (Sunnyvale, CA)
- …Join Meta's Wearable Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to develop cutting-edge AMS ... augmented reality systems. **Required Skills:** Digital Mixed Signal Design Engineer Responsibilities: 1. Collaborate with AMS architects to define… more
- Qualcomm (Santa Clara, CA)
- …. Working with the WiFi algorithm and systems team to design and test advanced WiFi functionalities such as OFDM and OFDMA modulators and demodulators, transmit ... beamforming, timing and synchronization, RF impairment correction, adaptive filters ....with the verification engineers to develop unit-level and integrated-level test -benches . Debugging the designs in stand-alone and integrated… more
- TrustPoint (Mountain View, CA)
- …anti-jam capabilities. The improvements will support US Government position and timing service resiliency as well as enable next-generation commercial applications ... with our microsatellite based commercial infrastructure and innovative positioning and timing services. The Position With locations outside Washington DC and in… more
- Amazon (Sunnyvale, CA)
- …around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of… more
- Teledyne (Mountain View, CA)
- …Electronic Warfare (EW/ECM/CIED), Industrial, Missile/UAV, Radar, Satcom, Space, and Test and Measurement. Teledyne Microwave Solutions invests heavily in research ... and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design of integrated circuits… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SoC Prototyping Engineer to continue to innovate on behalf of our customers. We are a part of ... ML accelerator at edge. As a Sr. SoC Prototyping Engineer , you will be part of a pre-silicon platform...on external lab equipment / daughtercards, completing partitioning / timing closure and performing bring-up and debug activities. You… more
- Arrow Electronics (San Jose, CA)
- … Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/ Test ) handling, block and top level static timing analysis, ECO ... generation at top level, handshaking with blocks for timing /functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to design ... micro-architecture and design including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools and using the latest… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and...define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need… more
- NVIDIA (Santa Clara, CA)
- …a wide range of sectors. We are seeking post-silicon Senior System Level Product Engineer who is passionate and committed to making a difference in the world through ... As a member of this team, you are responsible for developing procedures and test specs for manufacturing line with an innate understanding of product quality and… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3. ... selection and integration 6. Collaboration with verification and emulation teams in test plan development and debug 7. Collaboration with implementation team to… more
- Meta (Sunnyvale, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL development using ... selection and integration. 5. Collaboration with verification and emulation teams in test plan development and debug. 6. Collaboration with implementation team to… more