- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
- Meta (Sunnyvale, CA)
- …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design implementation ... logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology… more
- Meta (Sunnyvale, CA)
- …Join Meta's Wearable Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to develop cutting-edge AMS ... optimize state-of-the-art AMS IP's, while also supporting the development of next-gen custom mixed signal IC's for our industry-leading virtual and augmented reality… more
- Amazon (Sunnyvale, CA)
- …an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of ... the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design… more
- Google (Mountain View, CA)
- …low-power design techniques. + Experience with ARM-based SoCs, interconnects and ASIC methodology . + Experience with a scripting language like Python or Perl. ... interconnects or peripherals. + Experience with methodologies for low power estimation, timing closure, or synthesis. + Experience with methodologies for RTL quality… more
- Qualcomm (Santa Clara, CA)
- …full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is ... Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and power… more
- Cisco (San Jose, CA)
- …Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis * Past experience with Post silicon validation using DFT patterns. ... Tcl, Python/Perl. Preferred Qualifications: * Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification *… more