• CPU Physical Design

    Qualcomm (Austin, TX)
    …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
    Qualcomm (06/27/24)
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  • CPU Physical Design Engineer

    Qualcomm (Austin, TX)
    …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Engineer, you will work with microarchitecture and ... power implementation methods + Knowledge of CPU microarchitecture, logic design and circuits ** Physical Requirements** + Frequently transports between… more
    Qualcomm (09/07/24)
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  • Hardware ( CPU , GPU, SoC, Digital…

    Qualcomm (Austin, TX)
    … (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... coverage collection, gate level simulation, waveform viewers + C, C++, Python **_Digital Design /DV_** + RTL development for modem physical and MAC layer… more
    Qualcomm (08/20/24)
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  • CPU RTL Power Engineer

    Qualcomm (Austin, TX)
    … to meet targets working with architecture, RTL, verification and physical design teams * Create comprehensive CPU power models, identify early power targets ... power modeling and estimation experience. * Deep understanding of CPU or ASIC low power design including...and achieve correlation with physical design , and analyze power/performance/area tradeoffs *… more
    Qualcomm (06/13/24)
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  • CPU Systems RTL Engineer

    Qualcomm (Austin, TX)
    …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Experience with simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power implications. **Preferred… more
    Qualcomm (08/31/24)
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  • CPU Micro-architect/RTL Designer (Multiple…

    Qualcomm (Austin, TX)
    …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing more
    Qualcomm (08/09/24)
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  • Sr. Program Manager - CPU IP

    Qualcomm (Austin, TX)
    CPU Engineering team including the following responsibilities: * Work with Physical Design (PD) team to plan/track project execution from Synthesis through ... * Work closely with Release management team to ensure Physical Design Quality of the different designs...or more aspects of PD such as sign-off (PnR, timing ), physical verification, IR/EM is strongly preferred… more
    Qualcomm (07/12/24)
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  • Principal Physical Design Engineer

    Microsoft Corporation (Austin, TX)
    …this goal, Microsoft's Cloud Compute Development Organization (CCDO) is seeking a Physical Design (PD) CPU /High performance Intellectual Property (IP) ... at work and beyond. **Responsibilities** + Responsible for Core CPU (L1-L2) and/or non-Core/SOC Timing critical IPs'...signoff. + Demonstrate technical expertise across various domains of Physical Design & Timing Signoff… more
    Microsoft Corporation (09/05/24)
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  • Senior (Mil-Aero) RTL Design - Architect

    Cadence Design Systems, Inc. (Austin, TX)
    …verification and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, ... CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP + Design IP...and/or RISCV CPU and System IP + Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe,… more
    Cadence Design Systems, Inc. (06/18/24)
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  • GPU Implementation Engineer

    Qualcomm (Austin, TX)
    …the GPU. Understand the data flow across major buses and the implications for physical design , in particular for feedthroughs. + Identify issues and propose ... place-and-route methodologies to support higher clock frequencies. Minimum Qualifications + Physical design experience. + Bachelor's degree in electrical… more
    Qualcomm (07/30/24)
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