• Digital Integrated Circuit Design Engineer…

    The Boeing Company (Huntington Beach, CA)
    …industry standard Electronic Design Automation (EDA) tools and methodologies for digital ASIC / FPGA /SoC design and verification - eg Synopsys VCS, ... wafer fabrication but performs design (architecture, RTL, synthesis, circuits, physical design , verification , packaging and test) in house. SSED has numerous… more
    The Boeing Company (10/31/24)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Los Angeles, CA)
    …next chapter of your career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ ... research and development process from concept to field deployment. FPGA Design Engineers are responsible for the...+ RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification more
    Silvus Technologies (08/15/24)
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  • Application Engineer Consultant Functional…

    Siemens Digital Industries Software (El Segundo, CA)
    …of experience in EDA, or Semiconductor field. + A strong understanding of Design and Verification concepts in ASIC & FPGA flow is required. + Expert in ... Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies worldwide...Siemens EDA ICVS technologies in designing and verifying complex ASIC & FPGA designs for the most… more
    Siemens Digital Industries Software (10/25/24)
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  • Manager Electronics Engineering 3 - DICE Assistant…

    Northrop Grumman (Manhattan Beach, CA)
    …in Engineering + A minimum of 7 years of experience in digital unit, or ASIC / FPGA design + Prior leadership experience as a technical, program, functional ... Department - an organization of 100+ engineers that develops FPGA and ASIC Electronics for Space Systems,...but not limited to proposal and costing, requirements derivation, design , verification , and testing, with roles ranging… more
    Northrop Grumman (11/01/24)
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