- Cisco (San Jose, CA)
- …and noise, while managing ECO tasks. *Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and ... STA , along with advising the Physical Design team on...*Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to support ... can create as part of a world-class engineering team. **Required Skills:** ASIC Package Engineer SI/PI Responsibilities: 1. Drive chip-package-system co-design… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC.… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC.… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC.… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Meta (Sunnyvale, CA)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ASIC ... **Summary:** Meta is hiring ASIC Methodology Engineers within our Infrastructure organization to work on design integrity and signoff methodology development. We are… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- Broadcom (San Jose, CA)
- …**Senior Custom ASIC Engineering Lead** Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as ... physical design, STA , DFT, and packaging? Have you taped out so...ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in… more
- Amazon (Sunnyvale, CA)
- …front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining ... test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans - Write high quality documents to guide a scalable team Basic Qualifications - Bachelor's degree in Electrical Engineering, Communications Engineering or… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **Principle DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for ... phases of SoC DFT related activities for Broadcom APD ( ASIC Products Division)'s designs - DFT Architecture, Test insertion...metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. The position is part of Palladium ASIC development team . The team is responsible for all the ASICs that go into the ... of the usage modes and debug tools. The Palladium ASIC team has a wide range of expertise from...Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint… more
- Google (Mountain View, CA)
- …ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon ... a must. The Role: We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design, and methodologies including synthesis, place and route, … more
- MetaOption, LLC (Milpitas, CA)
- Physical Design Engineer Looking for someone with a wide range of pre-silicon experience. (Example's) - Validation, Implementation, CAD, Block level. We need someone ... years being the sweet spot. Overview: Seeking a hands-on Physical Design Engineer with 8-10 years of experience in pre-silicon validation, implementation, CAD, and… more
- NVIDIA (Santa Clara, CA)
- …industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams with advanced implementation ... experience; MS preferred + Be familiar with Verilog and ASIC design along with experience in commercial EDA tools... methodologies such as RTL Lint, CDC, DFT or STA . + Experience with compute farm interaction: software deployment,… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... and sign-of. tools in TCL, Perl, and/or Python - Solid understanding of ASIC physical design, physical design flows, and methodologies including synthesis, place and… more
- Google (Sunnyvale, CA)
- …clock verification, and signoff. Preferred qualifications: + Experience in ASIC physical design, physical design flows, and methodologies including synthesis, ... place and route, Static Timing Analysis ( STA ), formal verification, Change Data Capture (CDC), and power analysis. + Experience in IP integration (eg, Phase Lock… more