• ASIC Digital Physical

    Broadcom (San Jose, CA)
    …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
    Broadcom (11/01/24)
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  • ASIC and/or FPGA Design

    The Boeing Company (El Segundo, CA)
    …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... and test of ASIC /FPGA designs + 5 or more years of experience working with digital ASIC /FPGA design and verification + 5 or more years of experience with… more
    The Boeing Company (10/26/24)
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  • Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer...and CMOS solid state physics + Knowledge of CMOS digital design principles, basic standard cells their ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
    SpaceX (08/16/24)
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  • Intern ASIC Digital Design

    Micron Technology, Inc. (Minneapolis, MN)
    …communicate and advance faster than ever. **Position** **Description:** As a digital design engineer intern in Micron's ASIC logic design team, you ... candidate will be a curious driven individual looking to break into the high-speed ASIC design industry. **Responsibilities include, but not limited to:** + Be… more
    Micron Technology, Inc. (10/08/24)
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  • Senior E/E & Semiconductor Engineer - ASIC

    Capgemini (San Francisco, CA)
    ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... candidate should have a high aptitude for floor-planning the design of complex digital top level and/or...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
    Capgemini (10/16/24)
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  • ASIC Design Verification Engineer

    Cisco (San Jose, CA)
    …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching...develop innovative technology, and to power a more inclusive, digital future for everyone. How do we do it?… more
    Cisco (10/28/24)
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  • Senior ASIC Physical Design

    Capgemini (San Francisco, CA)
    **Job Title : Senior ASIC Physical Design Engineer**... and software to support the convergence of the physical and digital worlds. Coupled with the ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
    Capgemini (10/16/24)
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  • Sr. ASIC Design Verification…

    SpaceX (Irvine, CA)
    Sr. ASIC Design Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At...capabilities of the Starlink network. RESPONSIBILITIES: + Responsible for digital ASIC and/or FPGA verification at block… more
    SpaceX (10/17/24)
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  • ASIC Engineer Intern, Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which ... Engineering or related engineering fields 11. Experience with Lint, Synthesis, Formal or Physical Design tools 12. Scripting capability with Python or Perl 13.… more
    Meta (11/02/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …System-Verilog, with a good understanding of Computer Architecture and Digital Systems design . + A deep understanding of ASIC design flow including ... NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design...synthesis/timing clean design while working with the physical design team to ensure a routable… more
    NVIDIA (08/07/24)
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  • Sr. Technical Program Manager, ASIC

    Amazon (Redmond, WA)
    …of Silicon development from architecture definition, RTL design , Verification, IP design , Physical design , silicon bring up, test, characterization, ... around the world. Project Kuiper will help close the digital divide by delivering fast, affordable broadband to a...ASIC /SOC leads) to create project execution plans for ASIC /SOC development considering all criteria to design more
    Amazon (10/23/24)
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  • Sr. ASIC Physical Design

    Micron Technology, Inc. (Minneapolis, MN)
    …collaborative skills in this exciting and outstanding opportunity. We're looking for a Principal Physical Design Engineer ( ASIC ) to join our team! You will ... design , layout, and optimization of Memory/Logic/Analog circuits. + Chip floor-planning, physical design , IP integration, static timing analysis, design more
    Micron Technology, Inc. (08/07/24)
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  • ASIC Design for Test Technical…

    Cisco (San Jose, CA)
    …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
    Cisco (08/16/24)
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  • ASIC Engineer II (Intern) United States

    Cisco (San Jose, CA)
    …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... the latest deep submicron silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability to manage multiple tasks and… more
    Cisco (09/14/24)
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  • ASIC Engineer Intern, Implementation

    Meta (Sunnyvale, CA)
    …**Required Skills:** ASIC Engineer Intern, Implementation Responsibilities: 1. Participate in Design Implementation, Physical Design , and Design ... **Summary:** Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization....efficiently. You will have an opportunity to participate in design implementation/emulation, physical design , EDA… more
    Meta (11/04/24)
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  • ASIC Physical Design Engineer…

    Amazon (Austin, TX)
    …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis,...Spice Circuit analysis - Experience with Place and Route, digital implementation - Experience with EDA tools from Synopsys… more
    Amazon (10/04/24)
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  • ASIC Lead Engineer, Project Taara (Fixed…

    Google (Mountain View, CA)
    design will include analog mixed signal, radio frequency focused, and digital design for free-space optical communication links including; analog front-end, ... ASIC Lead Engineer, Project Taara (Fixed Term) Hardware...input from various teams, contribute to the detailed circuit design , own the foundry submission process, oversee physical more
    Google (10/18/24)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more
    Cisco (11/01/24)
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  • Sr. ASIC Implementation Engineer, DBF…

    Amazon (Redmond, WA)
    …Engineering. * 10+ years of experience in ASIC implementation. * Experience in leading physical design . * Strong exposure to UPF flow for low power design ... Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit...flow for various technology nodes. * Work with the ASIC design and DFT teams to understand… more
    Amazon (10/24/24)
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