- Meta (Harrisburg, PA)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Lockheed Martin (North Andover, MA)
- **Description:** Join Our Team as a ** ASIC /FPGA Verification Engineer ** where you will work on the development of a sophisticated state\-of\-the\-art ... at Lockheed Martin Space's Silicon Solutions team and seeking a future\-looking Principal Verification Engineer who is able to case and realize a compelling… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Performance & Package Verification Responsibilities:… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14.… more
- Meta (Sunnyvale, CA)
- …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Leverage Design ... towards creating a first-pass silicon success. 5. Furthermore, the ASIC Engineer , Design Verification will...stimulus, checkers, and reference models 18. Block/IP/SoC/full chip level verification 19. Formal property verification … more
- Palo Alto Networks (Santa Clara, CA)
- …and the kind of precision that drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ... You will work on diverse platforms including simulation, emulation, formal verification , and silicon validation. We expect...- MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in… more
- Cisco (Maynard, MA)
- …back to a company culture that empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Intern Engineer will be a member of a team ... a full-time undergraduate program + Knowledge of the latest ASIC verification methodologies,toolsand scripting/programming languages + Knowledge… more
- Northrop Grumman (Jessup, MD)
- …in Verilog, System Verilog or VHDL RTL + Circuit synthesis, formal verification , and static timing using state-of-the-art digital ASIC design tools + ... We are seeking a front-end ASIC design engineer for design and verification of full-custom...test plans. Must be knowledgeable in synthesis, SDC constraints, formal verification , and static timing. Knowledge of… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- Amazon (Sunnyvale, CA)
- …in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . Work ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year… more
- L3Harris (Herndon, VA)
- …and cyber domains in the interest of national security. Job Title: Sr. Specialist ASIC /FPGA Senior Design Engineer Job Code: 30428 Job Location: Herndon, VA ... customers in more than 100 countries. Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Design Engineer will be part of the key … more
- L3Harris (Camden, NJ)
- …land, sea and cyber domains in the interest of national security. Job Title: ASIC /FPGA Design Engineer (SMES) Job Code: 29446 Job Location: Camden, NJ Schedule: ... Preferred. + 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC /FPGA products. +… more
- Amazon (North Reading, MA)
- …digital verification , preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - ... highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team… more
- NVIDIA (Santa Clara, CA)
- …of our Memory Subsystem Design team, you will collaborate with architects/design verification / formal verification /physical design team to deliver a ... NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of… more
- Cisco (Maynard, MA)
- …Cadence Innovus or Synopsys ICC2 * Synthesis experience including Synopsys DC/FC * Formal Verification experience using tools such Synopsys Formality or Cadence ... networks. Acacia's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...team can provide. Your Impact As a Physical Design Engineer , you will play a key role in the… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA, you'll join a group of hardworking ... a fully verified, synthesis/timing clean design. + Collaborate with architects, verification engineers, formal engineers, physical design engineers, and software… more
- Meta (Sunnyvale, CA)
- …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems 9. Experience with Synthesis, Timing Closure and Formal Verification Methodology 10. Master's or PhD… more
- NVIDIA (Santa Clara, CA)
- …Strong proficiency in micro-architecture and RTL development using Verilog. + Experience with formal verification using JasperGold is a plus. + Deep expertise in ... We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA...groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's… more