- Meta (Austin, TX)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...equivalent practical experience. 9. 5+ years of experience in static verification tools 10. Experience with Lint, Clock Domain… more
- SpaceX (Irvine, CA)
- SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... enabling human life on Mars. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) At SpaceX we're leveraging our experience in… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...analysis , SI noise analysis 13. Experience with running Static Timing Analysis for full chip using DMSA 14.… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... of complex digital top level and/or blocks, with experience across the complete ASIC /SOC design flow including routing, static timing closure, EM/IR analysis and… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering ... area targets. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking,...path planning and crafting needed. + Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus.… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... timing convergence, timing constraints generation and management, and ECO generation and implementation . What we need to see: + BS (or equivalent experience) in… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more
- Qualcomm (San Diego, CA)
- …transformation to help create a smarter, connected future for all. Qualcomm's SoC Implementation Team is looking for skilled engineers to focus on timing constraints ... for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …fundamentals and Static Timing Analysis is required + Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with ... in the field of artificial intelligence and machine learning. Lead Application Engineer is responsible for providing pre-sales and post-sales technical support for… more
- IERUS Technologies, Inc. (Huntsville, AL)
- …blocks, both in the front-end and back-end with knowledge/experience across the complete FPGA/ ASIC /SoC design flow. The IC Design Engineer should also be ... more, please visit www.ierustech.com. Overview: As an Integrated Circuit Design Engineer specializing in radiation-hardened microelectronics, you will play a key… more
- Cisco (San Jose, CA)
- …Engineering or Computer Science, with 5+ year minimum of hands-on experience in ASIC implementation and Physical verification. * Hands-on experience in physical ... ASICs being developed. Your Impact As a physical design engineer you will be spearheading the implementation ...Science, with 3+ year minimum of hands-on experience in ASIC implementation and Physical verification. * Experience… more
- Micron Technology, Inc. (Atlanta, GA)
- …technology and growing upon your imagination and creativity. As a Principal RTL Design Engineer , you will be responsible for all aspects of DRAM digital IP design, ... from specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target...will be responsible for designing DRAM digital IPs with ASIC flows. You will implement, document and deliver high… more
- L3Harris (Camden, NJ)
- Job Title: Senior Electrical Engineer (FPGA Design) Job Code: 19447 Job Location: Camden, NJ Schedule: 9/80 Regular with every other Friday off Job Description: ... Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff (SMES) will...from system requirements + Develop detailed FPGA architecture for implementation + Implement design in RTL (VHDL) and perform… more
- Medtronic (Tempe, AZ)
- …* Generate DFT design for assigned System on Chip (SOC)/Application Specific Integrated Circuit ( ASIC ) based on product DFT requirements * Work as IC Design DFT Lead ... failure to root cause * Ensure all DFT design implementation meet the product DFT coverage goals * Maintain...years of relevant experience including experience in SOC and ASIC designs, or advanced degree with a minimum of… more
- Qualcomm (San Diego, CA)
- …Group, Engineering Group > GPU ASICS Engineering **General Summary:** QCT's Digital ASIC design team delivers cutting edge hardware and software products that power ... benches to verify complex designs in GPU. Position involves working with design, implementation teams to verify designs with high quality. Must be proficient in… more
- Micron Technology, Inc. (Richardson, TX)
- …the world uses information to enrich life. As an HBM SOC Physical Design Engineer , you will be responsible for the design & development of next-generation HBM DRAM ... only while the Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) of HBM...+ Completing various tasks in the netlist to GDSII implementation for partition(s), meeting schedule, and design goals. +… more
- Meta (Sunnyvale, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more