- Qualcomm (Santa Clara, CA)
- …flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support ... the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer,...our high-performance place-and-route CAD flow + Architect and recommend methodology improvements to ensure our silicon has the best… more
- Qualcomm (San Diego, CA)
- …(ECO) flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance and tools/flows ... Responsibilities:** * Leverages advanced knowledge of computer architecture, micro-architecture, logic design , circuits, and/or physical design to develop… more
- NVIDIA (Santa Clara, CA)
- …to work in a dynamic team Ways to stand out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, ... or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding...from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical … more
- Qualcomm (Folsom, CA)
- …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive implementation of...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Physical Design Clock Engineer, you will work with microarchitecture, RTL ... design , CAD, block level and top level physical design teams to create best in... clocking. + Drive overall clock generation and distribution methodology of CPU . + Work with CAD… more
- Qualcomm (Boxborough, MA)
- … Design (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... coverage collection, gate level simulation, waveform viewers + C, C++, Python **_Digital Design /DV_** + RTL development for modem physical and MAC layer… more
- Google (Austin, TX)
- …Lead the collaboration with RTL, design verification, and physical design teams to develop an efficient CPU implementation. + Drive performance ... clear precedent including Central Processing Unit ( CPU ) performance, micro-architecture design , tool infrastructure, and methodology . + Plan, drive, and… more
- Qualcomm (San Diego, CA)
- …Area:** Engineering Group, Engineering Group > SoC Architecture **General Summary:** As a CPU Performance and Power Analysis Engineer, you will be working on CPU ... standard benchmarks and workloads. Your responsibilities lie primarily in the physical interaction with devices to enable measurement and data collection. **Required… more
- Google (Mountain View, CA)
- …a related field, or equivalent practical experience. + 8 years of experience with physical design flow such as constraints, synthesis, floor planning, place and ... for timing and power convergence. + Drive or develop physical design timing convergence tools and flows...design timing convergence tools and flows for advanced CPU designs to achieve outstanding Power Performance Area (PPA).… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for multiple ...Electrical Engineering with a minimum of eight years of CPU /GPU/ASIC implementation + Proficiency in TCL scripting + Proficiency… more
- Qualcomm (San Diego, CA)
- …support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to ... will make regular contributions to the overall improvement in design methodology to drive productivity and quality...+ On-chip tightly coupled SRAM & L3 cache controller architecture/ design + Experience with x86 or ARM CPU… more
- Qualcomm (San Diego, CA)
- …support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to ... interfaces to the rest of the system such as CPU , DSP, Multimedia Processors and the engineer is expected...will make regular contributions to the overall improvement in design methodology to drive productivity and quality… more
- Broadcom (Fort Collins, CO)
- …strong technical hands-on competency in using leading edge physical design EDA tools in projects. + In-depth CPU /DSP architecture/algorithm working ... Key competencies required are: + Working experience in (digital) physical design implementation of large scale ASICs...advanced process nodes. + Opportunity to participate in innovation, design flow and methodology development to address… more
- Capgemini (Seattle, WA)
- **Job Role:** **SOC Design Verification Engineer** **Job location: Seattle WA** **Job Description:** We are looking for SOC Design Verification Engineer who can ... based on verification test plan. **Key Responsibilities:** + Drive Design Verification to closure based on defined verification metrics...8 to 10 years of hands-on experience in SystemVerilog/UVM methodology + Experience in one or more of the… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …of both small-scale and large-scale algorithms running on different computing systems ( CPU , GPU, ASIC, FPGA etc). These may include assessing the computing ... which are calibrated with experiments. Your responsibilities lie primarily in the physical interaction with devices to enable measurement and data collection and… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …of both small-scale and large-scale algorithms running on different computing systems ( CPU , GPU, ASIC, FPGA etc). These may include assessing the computing ... which are calibrated with experiments. Your responsibilities lie primarily in the physical interaction with devices to enable measurement and data collection and… more
- Cisco (San Jose, CA)
- …meet timing and performance requirements. * Help define, evolve, and support our design methodology . * Collaborate with the verification team on as-needed basis ... bugs and close code coverage. * Work closely with physical design team to close design...protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU 's is desirable. * Design experience with… more
- Siemens (Fremont, CA)
- …and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip ... design . We have a unique company culture. With its...of semiconductor IC industry - ASIC, SoC, Memory, Interconnect, CPU architectures, embedded systems + Ability to work in… more
- Siemens (Fremont, CA)
- …to build a career in a rapidly growing and constantly innovating Electronic Design Automation (EDA) industry? Do you enjoy working with cutting edge technology and ... for candidates who like to interact with and influence others, possess strong design and/or verification background, requiring both in depth knowledge of HDL and… more