- Qualcomm (Folsom, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
- Google (Mountain View, CA)
- … and power convergence. + Drive or develop physical design timing convergence tools and flows for advanced CPU designs to achieve outstanding Power ... equivalent practical experience. + 8 years of experience with physical design flow such as constraints, synthesis,... physical verification. + Experience in high speed design timing convergence and in Static … more
- Qualcomm (San Diego, CA)
- …and implement multi-core CPU operations for all Qualcomm Business Units. As a CPU Physical Design Engineer, you will work with microarchitecture and RTL ... power implementation methods + Knowledge of CPU microarchitecture, logic design and circuits ** Physical Requirements** + Frequently transports between… more
- Qualcomm (Santa Clara, CA)
- …highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work! As a CPU Physical Design Engineer, you will work with ... Knowledge of high performance and low power implementation methods + Knowledge of CPU microarchitecture, logic design and circuits Preferred qualifications + MS… more
- NVIDIA (Hillsboro, OR)
- …meet performance, timing and power targets. + Deliver a synthesis/ timing clean design while working with the physical design team ensuring a routable ... We are looking for a Senior CPU Design Engineer! NVIDIA is seeking...fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks.… more
- Qualcomm (Austin, TX)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer, you will work with ... + Experience with Synthesis, place and route and signoff timing /power analysis. + Knowledge of high performance and low... design , Circuits, CAD) to solve key physical design problems in CPU … more
- Qualcomm (Austin, TX)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Experience with simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power implications. **Preferred… more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- NVIDIA (Santa Clara, CA)
- …need to see: + BS or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding of logic optimization techniques and ... expertise to improve PPA (power, performance and area) on CPU designs by collaborating with logic designers, physical...from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for ... caches , working closely with the physical design team on implementation, synthesis and timing ...CPU team, you'll be a liaison between Logic design and Physical design teams… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330...basic soc architecture. Be able to work with Front-end design team to address timing , congestion and ... Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 /hr..../ RDL routing, power grid generation, full chip STA timing , DFT strategy planning, and final physical … more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Cadence Design Systems, Inc. (Austin, TX)
- …verification and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, ... CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP + Design IP...and/or RISCV CPU and System IP + Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe,… more
- SpaceX (Irvine, CA)
- …integrates design blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/ timing clean design + Participate in all phases of ASIC and/or ... FPGA design flow (eg synthesis, timing closure, formality...+ ASIC/SoC system integration experience + Experience with multicore CPU subsystem design + Experience with standard… more
- NVIDIA (Westford, MA)
- …designers to deliver best in class IP + partnering with our Physical Design team on partitioning, floorplanning and timing closure + providing design ... logic or lower layers of the OSI stack in general + in-depth understanding of physical design + strong working knowledge of Verilog or System Verilog + strong… more
- Broadcom (Fort Collins, CO)
- …strong technical hands-on competency in using leading edge physical design EDA tools in projects. . In-depth CPU /DSP architecture/algorithm working ... System-On-Chip ASICs. Key competencies required are: . Working experience in (digital) physical design implementation of large scale ASICs (Multi-100 million… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Chip, CPU Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA for ... work at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers are...tools including Genus Synthesis, Innovus P&R and Tempus Static Timing Analysis flows is expected. The Intern needs to… more
- Cisco (San Jose, CA)
- … design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * Triage, debug, ... participate in reviews * Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and...protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU 's is desirable. * Design experience with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …experience working on IC physical designs tools.Hands on experience using the above physical design tools for design closure and knowledge of physical ... critical step for various optimization objectives of a chip design , including timing (how fast a chip...variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, & AI. The work done… more
- General Motors (Mountain View, CA)
- …next-generation vehicles. We are seeking an experienced platform software engineer to design and develop platform software for ADAS embedded platform. Your expertise ... stack. **The Role:** As Staff Software Engineer, Platform, you will: + Design and code development of safety critical platform applications using C, C++14… more