- Qualcomm (San Diego, CA)
- …and implement multi-core CPU operations for all Qualcomm Business Units. As a CPU Physical Design Engineer, you will work with microarchitecture and RTL ... power implementation methods + Knowledge of CPU microarchitecture, logic design and circuits ** Physical Requirements** + Frequently transports between… more
- NVIDIA (Hillsboro, OR)
- …meet performance, timing and power targets. + Deliver a synthesis/ timing clean design while working with the physical design team ensuring a routable ... We are looking for a Senior CPU Design Engineer! NVIDIA is seeking...with architects, design engineers, verification engineers, and physical design engineers teams to accomplish your… more
- Qualcomm (San Diego, CA)
- … (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... coverage collection, gate level simulation, waveform viewers + C, C++, Python **_Digital Design /DV_** + RTL development for modem physical and MAC layer… more
- Qualcomm (Austin, TX)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Experience with simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power implications. **Preferred… more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- NVIDIA (Santa Clara, CA)
- …need to see: + BS or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding of logic optimization techniques and ... expertise to improve PPA (power, performance and area) on CPU designs by collaborating with logic designers, physical...from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for ... caches , working closely with the physical design team on implementation, synthesis and timing ...CPU team, you'll be a liaison between Logic design and Physical design teams… more
- NVIDIA (Santa Clara, CA)
- …aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts ... should be able to engage with multiple teams and design the GPU or CPU clocks to...other team members, we deliver clock information to GPU, CPU and SOC verification team, timing and… more
- Amazon (Portland, OR)
- …device physics, custom/semi-custom implementation techniques - Experience solving physical design challenges across various technologies such as CPU , DDR, ... generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate...pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification,… more
- Cadence Design Systems, Inc. (Austin, TX)
- …verification and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, ... CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP + Design IP...and/or RISCV CPU and System IP + Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe,… more
- Qualcomm (San Diego, CA)
- …also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power ... a smarter, connected future for all. QCT Memory Controller Design Team is looking for ASIC Design ...interfaces to the rest of the system such as CPU , DSP, Multimedia Processors and the engineer is expected… more
- NVIDIA (Westford, MA)
- …designers to deliver best in class IP + partnering with our Physical Design team on partitioning, floorplanning and timing closure + providing design ... logic or lower layers of the OSI stack in general + in-depth understanding of physical design + strong working knowledge of Verilog or System Verilog + strong… more
- Qualcomm (San Diego, CA)
- …+ Constraining and Timing Analysis experience + Physical Aware Synthesis + Physical Aware DFT + Physical Design + Clock tree Planning + Spine ... solutions for connecting various best in class IPs like CPU , GPUs, NSPs, Modems and to the latest best...Chip) which is highly floorplan driven. Also, as a Physical Architect engineer you will design architectures… more
- NVIDIA (Santa Clara, CA)
- …the summer) Potential Internships in this field include : + AI Developer Technology + ASIC Physical Design and Timing + GPU Verification and Design + ... CAD Skills: Catia, SiemensNX , Solidworks Creo + Understanding of VLSI design , computer architecture, computer arithmetic CMOS transistors, and circuits + Basic… more