- Cadence Design Systems, Inc. (Austin, TX)
- …and debug support + Physical design deliverables. Create functional timing constraints, synthesize RTL to ensure power and area targets are met and constraints ... Rich experience in IP creation and/or SoC and IP ( CPU , Memory, Interface) integration Expert in RTL ...Desirable: A Self-motivated person with good communication and design management skills Experience with Cadence front end toolset #LI-MA1… more
- Google (Mountain View, CA)
- …or equivalent practical experience. + 10 years of experience in high-performance CPU or AI accelerator logic/ RTL design including micro-architecture definition ... bonus, equity, or benefits. Learn more about benefits at Google. + Develop CPU subsystem front-end designs, emphasizing micro-architecture and RTL design for the… more
- Qualcomm (San Diego, CA)
- …+ Experience with system-level performance modeling and simulation + Knowledge of power management techniques and strategies + Experience with thermal analysis ... one of the following Qualcomm multi-disciplinary teams: System (architecture, modeling, power , thermal as well as silicon profiling ), Front-end Design… more
- Texas Instruments (Dallas, TX)
- …data movement, interconnect, safety, security, Realtime functionality, Multimedia, ARM CPU Cores, Vision analytics and camera/display interfaces IP needs within ... with processing through graphics, video, imaging etc and/or ARM CPU cores, that solve our customers' challenges primarily in...or enhance the micro-architecture for Digital IP blocks + RTL development and QC flows (Lint, CDC, synthesis) to… more
- Qualcomm (San Diego, CA)
- …+ Team develops and maintains the device drivers and firmware of the clock, PMIC ( power management integrated circuit), RPM (resource power manager) et al HW ... logic analyzer, JTAG), **SoC content developer** (SoC, C, assembly, subsystems - CPU core, multimedia, I/O, peripherals, DDR, wireless, modem), CPU content… more
- Meta (Sunnyvale, CA)
- … architecture, memory subsystems, Cache hierarchies, SoC integration flows and UPF based power management 13. Solid understanding of SoC architecture and Pre-Si ... able to debug through layers of SW applications to RTL FSDBs 3. Map Protocol Checkers, RTL ...scenarios on the Pre-Si platforms and generate data for Power & Performance of different IP Blocks 5. Bring-up… more
- Texas Instruments (Dallas, TX)
- …teams + Define or enhance the micro-architecture for Digital IP blocks + RTL development and QC flows (Lint, CDC, synthesis) to ensure superior IP quality ... silicon/application debug + Drive IP architectural optimization for area, power and performance improvements **Qualifications** **Minimum Requirements** + 10 years… more
- NVIDIA (Westford, MA)
- …Computing, Gaming, and Entertainment solutions. Tasks will include micro-architectural definition, RTL coding, logic debug, timing closure, power optimization ... generation of PCIE PL and DL + implementing readable, high-performance, area and power efficient RTL to achieve design targets, including upcoming performance,… more
- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + Drive physical design and timing of high-frequency and low- power CPU , GPU, DPU and SoCs at block level, cluster level, and/or ... level. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing… more
- Qualcomm (Austin, TX)
- …of related work experience. Preferred Qualifications + Experience with high-speed CPU /GPU implementation methodologies: floorplan, clocking, RTL , synthesis, P&R, ... GPU architecture, or ability to learn. + Understanding of power /thermal management . + Understanding of power...as Python and Tcl. + Experience in working with RTL design and architecture teams. + Strong communication and… more
- Micron Technology, Inc. (Boise, ID)
- …design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ... "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the… more
- NVIDIA (Santa Clara, CA)
- …micro-architecture to improve the state-of-the-art in GPU memory system and memory management optimizing along the axes of performance, power efficiency, ... in solving complex problems while optimizing performance, area, complexity, and power on leading-edge silicon processes. This GPU memory architecture team creates… more
- Amazon (Sunnyvale, CA)
- …video encoders/decoders, applied machine learning, ML accelerators, audio, wireless, sensors, power management , system performance benchmarking, etc. As part of ... video encoders/decoders, applied machine learning, ML accelerators, audio, wireless, sensors, power management , system performance benchmarking, etc. * Hands-on… more
- Meta (Columbus, OH)
- …with higher performance and lower energy consumption as compared to running them on the CPU /GPU of the server. This is an architect role in which you will be ... throughput, memory bandwidth and latency, evaluate performance v/s area v/s power tradeoffs. 3. Identify appropriate workloads and micro-benchmarks to be used… more
- Meta (Menlo Park, CA)
- …with higher performance and lower energy consumption as compared to running them on the CPU /GPU of the server. This is a architect role in which you will be defining ... computation throughput, memory bandwidth and latency 3. evaluate performance v/s area v/s power tradeoffs. 4. Drive the architecture definition of one or more of the… more
- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will drive physical design of high-frequency and low- power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with ... design, such as driving timing convergence, timing constraints generation and management , and ECO generation and implementation. + Work in a cross-functional… more