- SpaceX (Irvine, CA)
- …level front-end implementation from timing constraints development, synthesis, formal verification, power intent generation & validation + Develop block and ... of various IPs into RTL + Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flows +… more
- NVIDIA (Santa Clara, CA)
- … product needs. + Collaborate and Lead: Collaborate with system architecture, power architecture, ASIC, SW/FW, validation , and production teams throughout the ... industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team....design, and debugging. + Strong fundamentals in digital design, clock design, low power design, DVFS, noise,… more
- Micron Technology, Inc. (Richardson, TX)
- …expertise in one or more areas: Physical Synthesis, Floor-Planning, Place and Route, Power Grid, Clock Tree Synthesis, Static Timing Analysis for Partition Level ... to enrich life. As an HBM SOC Physical Design Engineer , you will be responsible for the design &...bottlenecks and propose innovative architectures to target best-in-class performance, power , cost, reliability and quality for Micron's HBM product… more
- Skyworks (Austin, TX)
- Staff Digital Design Engineer Apply now " Date:Oct 14, 2024 Location: Austin, TX, US Company: Skyworks If you are looking for a challenging and exciting career in ... world communicates. Requisition ID: 74380 Job Summary Seeking a digital design engineer with experience and interest in developing complex mixed-signal ICs for… more
- Broadcom (Irvine, CA)
- …power and low- power designs + Analyze and resolve Lint and Clock /Reset Domain crossing issues in the design + Collaborate with verification team on test ... RTL coding (Verilog HDL) and debugging skills Must have an understanding of low power design and validation techniques including UPF/CPF Must be familiar with… more
- Qualcomm (Austin, TX)
- …positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools ... Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM,...IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC… more
- Micron Technology, Inc. (Richardson, TX)
- …world uses information to enrich life. As an HBM SOC Design and Integration Engineer , you will be responsible for the design & development of next-generation HBM ... bottlenecks and propose innovative architectures to target best-in-class performance, power , cost, reliability and quality for Micron's HBM product portfolio.… more
- Qualcomm (San Diego, CA)
- …closely with RTL design, physical design teams to optimize area, performance and power . + Generate, review and validate clock domain crossing, design constraints ... team is seeking talented engineers to work on synthesis, timing constraints, formal verification, power analysis, STA and CLP for premium tier chips. This is a great… more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and… more
- Northrop Grumman (Linthicum, MD)
- …orders of magnitude less power than CMOS while running at significantly higher clock speeds. As an RF Design Engineer on our team, you'll work alongside ... systems. MDA is seeking a **Principal / Senior Principal RF MMIC Design Engineer ** with demonstrated ability to support our innovative MDA team in support of… more
- Qualcomm (San Diego, CA)
- …Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA, and timing closure for premium-tier chips. This is an ... Description: Principal Duties and Responsibilities** + Develop constraints for physical power -aware synthesis, setup for various modes/corners and low- power … more
- NVIDIA (Santa Clara, CA)
- …clock and power gating, clock sequencing, binning, and power throttling. + Hands-on validation experience with lab debugging and tools (oscilloscopes, ... Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.… more
- Amazon (Cupertino, CA)
- …to Global 500 companies trust our robust suite of products and services to power their businesses. Diverse Experiences AWS values diverse experiences. Even if you do ... responsibilities - integrate multiple subsystems into top level SOC, ensure correct clock /reset/functional/DFT signal routing - As a key member of the ASIC design… more
- Google (Sunnyvale, CA)
- …Engineering or Computer Science, with an emphasis on computer architecture. + Experience with low- power design techniques such as clock gating, power gating, ... scripting languages (ie Tcl, Python or Perl). + Experience in UPF for low- power design, including power intent specification, verification, and implementation. +… more
- Insight Global (St. Paul, MN)
- …with 3-12 years of experience to join their team. As an Analog Design Engineer , you will play a crucial role in enhancing our domestic ASIC capabilities for ... mixed-signal circuit blocks, including PLLs, DLLs, phase interpolators, high-speed clock distribution circuits, high performance amplifiers and comparators, high-speed… more
- Broadcom (San Jose, CA)
- …and route and/ or timing closure - floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification ... would also be required to do equivalence checks, STA, Timing closure and power optimization. Should be able to implement timing and functional ECOs. In this… more
- Micron Technology, Inc. (Dallas, TX)
- …are transforming how the world uses information to enrich life. As a Design Engineer at Micron, you will be responsible for crafting and analyzing digital and analog ... and sophisticated memory designs to product development, systems design, and validation resulting in outstanding memory solutions. In this position, you will… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction, power and UPF/CPF concepts. . Execute and ... -Signoff tool. Execute and deliver on timing analysis, ECO flows, Extraction, Power , EMIR and/or physical design and ensure integrity of delivered solutions.… more
- Qualcomm (San Diego, CA)
- …synthesis, special placement strategies, optimal floorplanning, special clocking solutions (like mesh clock tree), power planning and analysis for lower power ... latest best in class DDR. As a Qualcomm ASIC Engineer , you will plan, define, model, design, optimize, verify,...CTS + Custom Placement and Routing and Source Sync Clock Routing + Formal verification experience + Power… more
- Skyworks (Nashua, NH)
- …talented individuals who together can change the way the world communicates. High-performance clock ICs are the heartbeat of the internet. At Skyworks, the Timing ... role. Flexibility and creative problem-solving are key skills required in any applications engineer . This team directly supports a wide range of end customers and… more