• Clock / Power Validation

    Qualcomm (San Diego, CA)
    …/ or associated areas (SW development, embedded systems etc.) + Prior work experience in clock / voltage/ power validation is desired. + Knowledge of PMIC is ... connected future for all. **Team Details:** + **Qualcomm's SoC validation team** is an integral part of the **global...and maintains the device drivers and firmware of the clock , PMIC ( power management integrated circuit), RPM… more
    Qualcomm (06/06/24)
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  • Power Management Design engineer

    Qualcomm (Austin, TX)
    …for ASICs + Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains + Familiar with UPF and power ... AHB, AXI, SPMI, I2C, SPI + Experience in low power design methodology and clock domain crossing...related field and 4+ years of ASIC design, verification, validation , integration, or related work experience. OR Master's degree… more
    Qualcomm (05/11/24)
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  • Sr. Synthesis & Front-End STA Engineer

    SpaceX (Sunnyvale, CA)
    …of various IPs into RTL + Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flows + ... Sr. Synthesis & Front-End STA Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out… more
    SpaceX (05/09/24)
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  • Digital Design Engineer

    Skyworks (Austin, TX)
    Digital Design Engineer Apply now " Date:Jun 19, 2024 Location: Austin, TX, US Company: Skyworks If you are looking for a challenging and exciting career in the ... the world communicates. Requisition ID: 72122 Description Seeking a digital design engineer with experience and interest in developing complex mixed-signal ICs for… more
    Skyworks (05/15/24)
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  • Digital Design Engineer

    Skyworks (Nashua, NH)
    engineer developing complex mixed-signal ICs for frequency control, clock generation, network synchronization, and other timing applications. The candidate will ... Digital Design Engineer Apply now " Date:Jun 10, 2024 Location:...models/RTL, firmware, and behavioral models. Test bench development + Validation of silicon functionality, behavior, and performance Qualifications MS… more
    Skyworks (04/13/24)
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  • Physical Design Engineer

    Qualcomm (San Diego, CA)
    …help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, verify, validate, ... development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to… more
    Qualcomm (06/03/24)
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  • Hardware Design Engineer

    Capgemini (Santa Clara, CA)
    **Title: Hardware Design Engineer ** **Location: Santa Clara, CA** **Duration: Full Time** **Position Description:** **About the Role:** . Experience in high-speed ... hardware designs, testing, validation of Networking products . Having good knowledge on...availability of the products . Experience in Analog/Mixed circuits, Power circuit designs . Good problem solving and complex… more
    Capgemini (06/20/24)
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  • Senior Post Silicon Hardware Engineer

    NVIDIA (Santa Clara, CA)
    clock and power gating, clock sequencing, binning, and power throttling. + Hands-on validation experience with lab debug and tools (oscilloscopes, ... level post silicon bring-up and debug. + Experience in Silicon DFT bring up/ validation . Experience in optimizing quality of silicon vs other trade offs like cost.… more
    NVIDIA (05/26/24)
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  • Principal HBM DFT Design Engineer

    Micron Technology, Inc. (Folsom, CA)
    …information to enrich life. We are looking for a HBM DFT Design Engineer . Are you passionate about system and architecture for next generation of high-performance ... across memory and storage solutions. **Our Opportunity Summary** As an HBM DFT Design Engineer you will work in an innovative and dynamic team and will be… more
    Micron Technology, Inc. (05/18/24)
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  • SOC Implementation Engineer

    Qualcomm (San Diego, CA)
    …closely with RTL design, physical design teams to optimize area, performance and power . + Generate, review and validate clock domain crossing, design constraints ... team is seeking talented engineers to work on synthesis, timing constraints, formal verification, power analysis, STA and CLP for premium tier chips. This is a great… more
    Qualcomm (06/27/24)
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  • Sr. ASIC Design Engineer , DDR IP (Silicon…

    SpaceX (Irvine, CA)
    Sr. ASIC Design Engineer , DDR IP (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER , DDR IP (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building… more
    SpaceX (06/28/24)
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  • Design Engineer

    The Boeing Company (Kirtland AFB, NM)
    …& Security (BDS) has an exciting opportunity for an **Electrical Design Engineer ** to support the development of electro-optical systems at the Starfire Optical ... with basic test devices (ie, Voltmeter, DMM, logic analyzer, oscilloscope, clock generators, function generators). + Ability to gather requirements, develop designs,… more
    The Boeing Company (06/04/24)
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  • Principal High Speed Design Engineer - HBM…

    Micron Technology, Inc. (Atlanta, GA)
    …uses information to enrich life. We are looking for an HBM High-Speed Design Engineer . Are you passionate about designing circuits for the next generation of memory ... that will power groundbreaking AI applications? You will work in an...on the gate-level design only. Lastly, verification and testing ( validation ) of HBM is the most challenging due to… more
    Micron Technology, Inc. (05/16/24)
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  • Sr. FPGA/ASIC Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …FPGAs PREFERRED SKILLS AND EXPERIENCE: + Ability to solve complex problems including clock domain crossings and power optimization + ASIC/SoC system integration ... Sr. FPGA/ASIC Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the… more
    SpaceX (05/17/24)
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  • CPU RTL Engineer

    Qualcomm (Santa Clara, CA)
    …timing and power implications. **Roles and Responsibilities** As an RTL engineer you will own or participate in the following: + Performance exploration. Explore ... for CPU RTL development targeted for high performance, low power devices. In this role, you will work with...work experience with simulation, emulation, formal verification, or silicon validation . + 1+ year of experience in creating functional… more
    Qualcomm (06/30/24)
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  • Senior System Integration Engineer

    NVIDIA (Santa Clara, CA)
    clock and power gating, clock sequencing, binning, and power throttling. + Hands-on validation experience with lab debugging and tools (oscilloscopes, ... Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.… more
    NVIDIA (06/15/24)
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  • ASIC Design Engineer , Hardware Compute…

    Amazon (Sunnyvale, CA)
    …accelerators - Experience working with RISC-V - SOC bring-up and post silicon validation experience - Experience with early power analysis - Architecture/System ... Description As a ASIC Design Engineer , you work with a team creating hardware...software and verification to develop IP that meets the power , performance and area goals for Amazon devices. You… more
    Amazon (06/21/24)
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  • Senior Analog/mixed-signal IC Design…

    Cisco (San Jose, CA)
    …over PVT (monte-carlo analysis) -Electromigration analysis (using Totem, or equivalent) - Power and IR drop analysis Laboratory Validation : -Solid ESD ... will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met. Who you'll work with: You will work with… more
    Cisco (05/28/24)
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  • Senior FPGA Engineer

    Vector Atomic (Pleasanton, CA)
    …come join our team! Position Summary We are seeking a Senior FPGA Engineer interested in developing the next generation of quantum technology. This hands-on role ... part selection (along with support ICs such as memory, power supplies and Interface ICs) + Assist hardware developers...electronics; develop test scripts and documentation to assist with validation What We're Looking For + BSEE/MSEE Degree with… more
    Vector Atomic (06/08/24)
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  • ASIC Design Engineer (Security Group)

    Qualcomm (San Diego, CA)
    …solutions and products are elegantly engineered for optimal performance and power consumption. Our system-on-chip solutions like Snapdragon bring together CPU, GPU, ... of ASIC design flow: Architecture, Microarchitecture, verilog/system-verilog RTL design, Clock Domain Crossings, DFT, synthesis, and timing closure + Problem… more
    Qualcomm (06/07/24)
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