- Amazon (San Diego, CA)
- …that is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer - STA to continue to innovate on behalf of our customers. We ... signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital...& Route and other local/remote teams to address the design challenges in the context of timing sign-off. -… more
- Broadcom (Fort Collins, CO)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** STA Design Engineer :** **Technical Skills/ background:** Strong ... understanding of VLSI and ASIC physical design - Should have basic understanding of PLLs and...to generate and understand timing reports Understanding of basic STA concepts - Solid understanding of RC networks and… more
- Qualcomm (San Diego, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks. + Generate/review,… more
- SpaceX (Irvine, CA)
- …to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA /Timing Engineer /Level I: $120,000.00 - $145,000.00/per year ... Physical Design STA /Timing Engineer /Level II: $140,000.00 - $170,000.00/per year Your actual level and base salary will be determined on a case-by-case basis… more
- NVIDIA (Westford, MA)
- …to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class CDC/ STA Design Engineers to join our outstanding Networking Silicon ... + You will play a major role analyzing the design and driving fixes as well as developing, maintaining,...(CDC), Reset Domain Crossing (RDC) and Static Timing Analysis ( STA ) constraints and methodology for our DPUs and SOCs… more
- Cisco (San Jose, CA)
- … STA flow development, convergence strategies, and correlation between PNR, Spice, and STA , along with advising the Physical Design team on best practices. * ... Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues,...and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should be able to ... feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc. Job Responsibilities:… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …experience with Timing, Emir, Characterization & Simulation tools, and good circuit design knowledge to help enable Signoff solutions at customer site. Also, close ... and differentiating technologies.. + In this role, the Solutions Engineer (SE) is expected to work both independently and...for myriad circuits including memory designs and mixed signal design + The SE will participate in technical benchmarks,… more
- Qualcomm (Austin, TX)
- …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design ... primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU...out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.… more
- SpaceX (Irvine, CA)
- …computer science + 5+ years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC multimode ... deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer /Senior: $170,000.00 - $230,000.00/per year Your actual level and… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...block and chip level + Understanding constraints and fixing design /timing techniques + Block level implementation from netlist to… more
- Amazon (Cupertino, CA)
- …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and ... ASIC physical design , and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level of expertise in PD… more
- Broadcom (Irvine, CA)
- …STA , RTL/gate level simulations & silicon debug + Scripting for various IC design tasks such as STA , equivalency checks, test bench, simulations, synthesis, ... Products for High Speed Optical Communication. + architect block level design specifications from the marketing requirements and/or system requirements + prepare… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... You'll Be Doing: + Develop and validate flows for PT- STA regression, analysis, QOR metrics for high-speed designs. The...drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** **Technical Skills/ background:** The Design Architect/ Lead will lead a small team of engineers to interact ... will lend itself to seamless closure in the physical design backend flows, help define and influence sub-system content...to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC networks and… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
- Broadcom (Fort Collins, CO)
- …before you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure - ... Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able...In this role, the candidate will apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous… more
- ManpowerGroup (Santa Clara, CA)
- Our client in the technology industry is seeking an ASIC/RTL Design Engineer to join their team. As an ASIC/RTL Design Engineer , you will be part of the ... understand tools used by ASIC engineers like Lint, CDC, STA . If you possess these skills, we encourage you...to apply for this exciting opportunity. **Job Title:** ASIC/RTL Design Engineer **Location:** Santa Clara, CA (100%… more
- Northrop Grumman (Baltimore, MD)
- …you to join our team as a Principal Digital Engineer /Senior Principal Digital Engineer (FPGA and ASIC Design ) based out of Linthicum, MD. **What You'll get ... FPGA and ASIC product development. + Work closely with design engineers and will utilize your knowledge of modern... tools for synthesis, LEC, CDC + Experience with STA constraints generation and timing closure + Experience with… more