- BAE Systems (San Diego, CA)
- …self-checking testbenches in SystemVerilog/ UVM , OVM, and/or VHDL + Experience with FPGA /ASIC design and verification tools (Mentor Questa or Cadence) + ... **Job Description** Picture yourself developing advanced electronic systems deployed to protect members of...your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan,… more
- RTX Corporation (Tucson, AZ)
- …(3) of the following: + FPGA design (VHDL and/or Verilog coding) or FPGA verification (SystemVerilog coding) + Xilinx or Microsemi devices and flow tools + ... processors + Gigabit serial interfaces and multi-gigabit transceivers (MGTs) + Constrained random verification in UVM using System Verilog + Verification … more
- L3Harris (San Diego, CA)
- …HDL code for module and top level and generate appropriate testbench and verification environments. + Map FPGA simulation work products to system-level ... Job Title: Lead, FPGA Design Engineer - Technical Lead (Secret Clearance)...directly involved in the design, integration, and test of advanced satellite communication links, digital telemetry, signal processing, and… more
- BAE Systems (Nashua, NH)
- …(C/C ) + Scripting skills (Perl, Python, bash, Tcl) + Exposure to Design Verification methodologies such as UVM /OVM + Experience with Earned Value Management is ... **Job Description** BAE Systems is seeking FPGA Design Managers! Because this role involves a...engineers. Our employees work on the world s most advanced electronics from detecting threats for F-35 pilots to… more
- RTX Corporation (Tucson, AZ)
- …vendors, and executive leadership + Translate system-level requirements into FPGA requirements + Create documentation including requirements, verification ... Minimum of ten (10) years of applicable experience in FPGA design, verification , and integration to include...Gigabit serial interfaces and multi-gigabit transceivers (MGTs) + Assertion-based verification and UVM using System Verilog +… more
- BAE Systems (Nashua, NH)
- …generating scripts (Perl, Tcl, Python, shell, etc.) + Working knowledge of UVM /SystemVerilog and familiarity with design verification + Working knowledge of ... BAE Systems has an open position for a Principle FPGA Digital Design Engineer! See what you re missing....missing. Our employees work on the world s most advanced electronics from detecting threats for F-35 pilots to… more
- Cisco (Milpitas, CA)
- …or relevant degree and 3+ years of related experience. * Experience with UVM and/or VMM Verification methodology. * Experience with high-speed design debug. ... networking system requirements, mapping them into functional blocks for FPGA implementation, working with the cross functional team to...* Experience with advanced microprocessor-based design. This is an onsite role and… more
- Cisco (Milpitas, CA)
- …years of related experience. * Experience with UVM and/or VMM Verification methodology. * Experience with advanced microprocessor-based design. * Experience ... networking system requirements, mapping them into functional blocks for FPGA implementation, working with the cross functional teams to...that designs the ASR8000 routers as part of the FPGA team designing control path FPGAs for the various… more
- BAE Systems (Westminster, CO)
- …digital electronics, FPGAs, and embedded processor systems. + Experience with OVM/ UVM Verification methodologies. + Experience developing specifications, cost, ... of R&D, proof of concept, and production programs. + FPGA development and digital IP integration for tactical RF,...US Department of Education. + Digital system partitioning and advanced function implementation in FPGAs. + Solid electronic circuit… more
- Northrop Grumman (Linthicum, MD)
- …of our cross-discipline engineering team in Mission Systems that encompasses Digital Verification Engineering to support ASIC and FPGA product development. + ... complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. +...reviews, test development and RTL debug **Preferred Qualifications:** + Advanced Degree with at least 3+ years of professional… more
- Capgemini (Santa Clara, CA)
- …*Architect and Create verification environments using System-Verilog and Universal verification methodology- UVM IPs and SoCs with embedded CPUs and analog ... & System Verilog. * Strong knowledge in SV Assertions, UVM /OVM and functional code coverage. * SOC Verification...using ARM Cortex Microcontroller is required. * Experience with advanced peripheral bus Verification IP's such as… more
- Northrop Grumman (Linthicum, MD)
- …and HVL (SystemVerilog). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash,… more
- Northrop Grumman (Linthicum, MD)
- …can be used in Lieu of a BS degree + Advanced Knowledge of UVM and use of a coverage-driven verification methodology + Experience developing test plans, ... NGMS, Digital Technologies Group, is seeking a Staff Digital Verification Engineer to support ASIC and FPGA ...complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilog. This… more
- Northrop Grumman (Linthicum, MD)
- …and HVL (SystemVerilog). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... (SystemVerilog) + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Familiarity with a coverage driven … more
- Teradyne (North Reading, MA)
- …assertions + Porting tests from simulation to lab + Leading IP, ASIC or FPGA verification projects + Developing verification schedules for complex projects ... involved in all phases of development, including specification, architecture, design, verification , and silicon bring-up, focusing on developing UVM -based… more
- BAE Systems (Manchester, NH)
- …split between working onsite and remotely. BAE Systems is seeking a Design Verification Manager to work within our Electronic Systems business area leading a Design ... Verification (DV) group. We are interested in candidates with...engineering teams through all phases of an ASIC or FPGA development lifecycle is important, as the individual will… more
- Huntington Ingalls Industries (Roanoke, VA)
- …Matlab, etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface, and transaction levels, ... can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs....Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Active Secret… more
- Qualcomm (Santa Clara, CA)
- …+ Creates and maintains verification test benches and environments in System Verilog/ UVM + Create and leverage advanced testing frameworks to generate and ... optimizes performance and power of GPU cores. Responsible for verification of Graphics IP , and performing pre- and...Scripting, Simulation, problem solving and debug. + System Verilog, UVM , Verilog or VHDL, C/C++ skills required. + Constrained… more
- Siemens Digital Industries Software (El Segundo, CA)
- … concepts in ASIC & FPGA flow is required. + Expert in Advanced Verification methodologies & environments is essential. + Expert in coding with ... ICVS technologies in designing and verifying complex ASIC & FPGA designs for the most advanced Aerospace...Verilog/VHDL/SystemVerilog, UVM , PSL/SVA is mandatory. + Experience with … more
- SpaceX (Redmond, WA)
- …and capabilities of the Starlink network. RESPONSIBILITIES: + Responsible for digital ASIC and/or FPGA verification at block and system level + Write and review ... degree in electrical engineering or computer engineering + Experience with verification methodologies such as UVM /OVM/VMM + Strong object-oriented programming… more