- Qualcomm (San Diego, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Amazon (San Diego, CA)
- …that is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer- STA to continue to innovate on behalf of our customers. We are a ... Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk...& Route and other local/remote teams to address the design challenges in the context of timing … more
- ManpowerGroup (Phoenix, AZ)
- …STA /Synthesis Engineer** Required Skills: + Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic ... synthesis, design for testability, constraints, static timing analysis,...ECO in advanced technology nodes + Develop & document STA & Synthesis strategies. Interact with methodology teams to… more
- SpaceX (Irvine, CA)
- …in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. + Experience with power intent ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In… more
- Qualcomm (Austin, TX)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- NVIDIA (Santa Clara, CA)
- …improvements and solutions and deploy newer features. + Lead implementation of STA solutions for multiple circuit design and technology teams and 3rd party ... circuit IP. + Support SRAM and other custom circuit design engineers through successful timing convergence towards...closure experience with successful tapeouts. + Expertise in Static Timing Analysis and prior working experience with STA… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... you will be doing: + You will drive physical design and timing of high-frequency and low-power...including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation .… more
- Meta (Sunnyvale, CA)
- …20. 5+ years of experience in Design Integration and Front-End Implementation . 21. Synthesis Background, Timing Constraints Development, Floorplanning and ... and the corresponding reset sequence for RDC. 8. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for...Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 11. Work closely with the Design… more
- Google (Mountain View, CA)
- …Tree Synthesis (CTS), Design For Test (DFT) (Scan, MBIST, BISR), Static Timing Analysis ( STA ), signal/power integrity (SI/PI), Layout Versus Schematic and ... Design For Test (DFT). + Experience in sign-off convergence including Static timing analysis ( STA ), electrical checks, and physical verification. + Experience… more
- Meta (Sunnyvale, CA)
- …to develop reset groups and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level ... online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization techniques… more
- Qualcomm (San Diego, CA)
- …SoC implementation team is seeking talented engineers to work on synthesis, timing constraints, formal verification, power analysis, STA and CLP for premium ... chips. This is a great opportunity to join Snapdragon implementation team responsible for SoCs in sub-3nm nodes in...power. + Generate, review and validate clock domain crossing, design constraints to achieve timing closure of… more
- Cadence Design Systems, Inc. (Austin, TX)
- …Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best ... related experience in design and EDA (Digital Implementation /Signoff) + Understands ASIC Design implementation...+ Experience with EDA tools in the IC digital implementation & signoff flows ( STA tools) +… more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more
- Honeywell (Moca, PR)
- …Manufacturing (HVM) testing of the design . * Development of the Static Timing Analysis ( STA ) constraints for physical construction and timing closure ... You will play a pivotal role in driving the design and implementation of these circuits, contributing...in all DFT modes, and association with the Physical Design team to achieve timing closure for… more
- ManpowerGroup (Phoenix, AZ)
- …signoff, including power gating, multiple voltage rails, and UPF/CPF usage + Power grid design & implementation + Power integrity analysis at block and top ... **Job Title:** **Physical Design -Power Integrity Flow Development Engineer** **Location:** + **Primary:**...to gate-level netlist. + Develop and own power grid implementation for multi-hierarchy low power designs, including power analysis,… more
- Qualcomm (San Diego, CA)
- …methodologies + SOC Design implementation /methodology + Process technology + Circuit Design + STA timing + Power analysis + Semi-custom design ... * Consults with internal or external users and third-party vendors to guide implementation and ensure alignment with their needs and goals. * Builds deep… more
- Ford Motor Company (Dearborn, MI)
- …HLM System Design and Release Engineer is responsible for the design , development, validation, release and implementation of handles, locks, and mechanisms ... side doors, tailgates, liftgates, decklids). You will also drive for design improvements to increase quality and optimize cost/weight throughout development as… more
- Northrop Grumman (Baltimore, MD)
- …Special Program Access (SAP) prior to start. + Experience with industry standard FPGA design implementation tools for IP integration, PnR, CDC such as Xilinx ... + Working knowledge of full product life cycle (requirements, design , implementation and test) of FPGA ... tools for synthesis, LEC, CDC + Experience with STA constraints generation and timing closure +… more
- Ford Motor Company (Dearborn, MI)
- …you ready to change the way the world moves? **Product Development** uses design thinking & user experience methods to deliver breakthrough products and services ... Powerpack organization. The successful candidate will be responsible for the design and release activities associated with hot and cold-end exhaust… more
- Renesas (Austin, TX)
- …design constraints and handing off to P&R teams. + ** Timing Closure & Low-Power Design :** Proficient in STA and timing closure, as well as low-power ... **RTL Design :** Lead and oversee digital RTL design , ensuring compliance with timing , area, power,...+ **DFT & Layout:** Contribute to DFT strategy and implementation , review test case development, and collaborate with P&R… more