- Qualcomm (San Diego, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Amazon (San Diego, CA)
- …that is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer- STA to continue to innovate on behalf of our customers. We are a ... Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk...& Route and other local/remote teams to address the design challenges in the context of timing … more
- Broadcom (Fort Collins, CO)
- …a Candidate Account, please Sign-In before you apply.** **Job Description:** ** STA Design Engineer:** **Technical Skills/ background:** Strong understanding of ... timing tool - Ability to generate and understand timing reports Understanding of basic STA concepts...intangibles along with an in-depth understanding of the underlying design / constraints and implementation techniques used. Exercises… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post-sales activities ... Digital IC products. The qualified candidate will have hands-on experience with Timing , Emir, Characterization & Simulation tools, and good circuit design … more
- SpaceX (Irvine, CA)
- …to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA / Timing Engineer/Level I: $120,000.00 - $145,000.00/per year ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer...Physical Design STA / Timing Engineer/Level II: $140,000.00 - $170,000.00/per year… more
- SpaceX (Irvine, CA)
- …in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. + Experience with power intent ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In… more
- Qualcomm (Austin, TX)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- NVIDIA (Santa Clara, CA)
- …improvements and solutions and deploy newer features. + Lead implementation of STA solutions for multiple circuit design and technology teams and 3rd party ... circuit IP. + Support SRAM and other custom circuit design engineers through successful timing convergence towards...closure experience with successful tapeouts. + Expertise in Static Timing Analysis and prior working experience with STA… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... you will be doing: + You will drive physical design and timing of high-frequency and low-power...including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation .… more
- Broadcom (Fort Collins, CO)
- …Sign-In before you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to place and route and/ or ... Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should...considered for this position. Candidate should extremely proficient in design implementation activities both at block and… more
- Meta (Sunnyvale, CA)
- …20. 5+ years of experience in Design Integration and Front-End Implementation . 21. Synthesis Background, Timing Constraints Development, Floorplanning and ... and the corresponding reset sequence for RDC. 8. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for...Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 11. Work closely with the Design… more
- Qualcomm (San Diego, CA)
- …static timing analysis ( STA ) for complex digital designs. - Collaborate with design , verification and PD teams to ensure timing closure and design ... STA scripts and methodologies. - Analyze and resolve timing issues, working closely with cross-functional teams. - Run...power checks and Logic equivalency checks. - Participate in design reviews and provide feedback on timing … more
- Broadcom (San Jose, CA)
- …error messages from the timing tool - Ability to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC ... analysis, and other timing checks - Ability to understand and create timing diagrams Deep understanding of more advanced STA concepts - POCV/SOCV/LVF… more
- Capgemini (San Francisco, CA)
- …Physical Verification at both block and chip level *Understanding constraints and fixing design / timing techniques *Block level implementation from netlist to ... level and/or blocks, with experience across the complete ASIC/SOC design flow including routing, static timing closure,...PnR, CTS, block integration and ECO generation. *Expertise in timing closure ( STA ) of high frequency blocks… more
- Capgemini (San Francisco, CA)
- …Verification at both block and chip level + Understanding constraints and fixing design / timing techniques + Block level implementation from netlist to ... **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)**...CTS, block integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks… more
- Amazon (Redmond, WA)
- …to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC ... equivalent experience. * 7+ years of experience in ASIC implementation , ie, synthesis, STA and working with...Communications Engineering. * 10+ years of experience in ASIC implementation . * Experience in leading physical design .… more
- Qualcomm (San Diego, CA)
- …Aware Conformal Logic Equilalency Check: both RTL 2 Gate and Gate 2 Gate. + Run STA on final netlist and support PD timing /congestion closure + Work with RTL ... As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and...RTL designers on managing complex power intent + Manage timing constraints + Trouble shoot upf issues in synthesis… more
- NVIDIA (Santa Clara, CA)
- …logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation and ... understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure. + Experience in...and/or flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints… more
- Qualcomm (San Diego, CA)
- …SoC implementation team is seeking talented engineers to work on synthesis, timing constraints, formal verification, power analysis, STA and CLP for premium ... chips. This is a great opportunity to join Snapdragon implementation team responsible for SoCs in sub-3nm nodes in...power. + Generate, review and validate clock domain crossing, design constraints to achieve timing closure of… more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more