- Qualcomm (San Diego, CA)
- … ASIC engineers with excellent analytical and technical skills, and a focus on low power , high performance ASIC designs, and, ability to execute critical ... low power designs. + Strong knowledge in the entire low power , high performance ASIC /SoC design flows (micro-architecture, RTL design, verification,… more
- Meta (Austin, TX)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Work with Architecture and ... **Summary:** Meta is hiring ASIC Power Engineers within our Infrastructure...abstraction: C-model, RTL, Gate, Layout 6. Optimize design for low - power with the understanding of system level… more
- The Boeing Company (Kent, WA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will lead ... processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. Plus, we're applying the latest...determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance + Implement FPGA/ ASIC … more
- SpaceX (Irvine, CA)
- … power intent verification and post synthesis timing validation flows + Execute low power design and physical synthesis, deploying knowledge of unified ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...flow, top-down and bottom-up design methodologies + Knowledge of low - power methodologies and leakage/dynamic power … more
- Qualcomm (San Jose, CA)
- …to help create a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design, optimize, verify, validate, implement, ... IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional… more
- Amazon (Austin, TX)
- Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...ownership and deliveries * 3+ years of experience with power analysis and optimization * Experience working with SOC… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning. 19. Experience with low power implementation, power gating,… more
- Capgemini (San Francisco, CA)
- …complex designs - 1M instances and clock frequencies about 1 GHz *Experience with low power implementation and signoff, power gating, multiple voltage rails, ... **Physical Design Engineer ** **Job Description:** **The ASIC Physical...Responsibility:** *Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Power , Performance, Area Analysis and techniques for reducing power . 25. Knowledge of Low power… more
- Amazon (San Diego, CA)
- …implementation. * Experience in leading physical design. * Strong exposure to UPF flow for low power design. * Strong written and verbal skills * Experience of ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design… more
- Capgemini (San Francisco, CA)
- …designs - 1M instances and clock frequencies about 1 GHz + Experience with low power implementation and signoff, power gating, multiple voltage rails, ... **Job Title : Senior ASIC Physical Design Engineer ** **Job Location:...+ Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO… more
- Amazon (San Diego, CA)
- …and underserved communities around the world. Come work at Amazon! We're hiring a Modem Engineer within a high performance ASIC design team. This team is using ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...to chip specification to RTL to optimizing timing / power to chip level validation. . Develop solutions optimizing… more
- Actalent (Morrisville, NC)
- …of this position entails executing IC layout of cutting edge, high-performance, high-speed, low power CMOS Interface D2D and SERDES integrated circuits in ... ASIC /IC Layout Design Engineer - REMOTE Summary: Microsoft Silicon Team is continuing to revolutionize consumer electronic devices & Cloud Computing. This group… more
- Actalent (Morrisville, NC)
- …of this position entails executing IC layout of cutting edge high-performance high-speed low power CMOS Interface D2D and SERDES integrated circuits in foundry ... 100% Remote ASIC Design Opportunity!! NOTE: START DATE IS JANUARY...We are looking for an experienced Mask Layout Design Engineer who is innovative and has a passion for… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... What you'll be doing: + You will drive physical design of high-frequency and low - power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level,… more
- Amazon (North Reading, MA)
- …our customers love. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology....plans - Develop automated software test applications for effective ASIC stress testing - Collaborate with firmware teams to… more
- NVIDIA (Westford, MA)
- …will be doing: + You will drive physical design and timing of high-frequency and low - power DPUs and SoCs at block level, cluster level, and/or full chip level. ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering… more
- Amazon (North Reading, MA)
- …our customers love. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology....3+ years of demonstrable experience as a computer hardware engineer . - Strong knowledge of hardware design principles, testing… more
- Amazon (North Reading, MA)
- …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Evaluate 3rd party IP blocks - Estimate power ,… more
- Amazon (Austin, TX)
- …any necessary support logic . Configure, instantiate and integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...to develop world-class SOC and IP blocks, which meet power , area and performance targets. . Define, configure and… more