• Physical Design Engineer

    Cadence Design Systems, Inc. (Cary, NC)
    design . As well as participating in or leading next generation PHY IP physical design , methodology and flow development, the candidate will work closely with ... tapeouts.Main Job Tasks and Responsibilities: -Participating in or leading next-generation physical design , methodology, and flow development in advanced… more
    Cadence Design Systems, Inc. (11/21/24)
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  • Member of Technical Staff Physical

    onsemi (Richardson, TX)
    …engineering. **Responsibilities:** As a Member of Technical Staff Physical Design / PnR (Place and Route) Engineer , you will design custom ASSPs and ... Technical Staff Physical Design / PnR (Place and Route) Engineer , you are...Technical Staff Physical Design / PnR (Place and Route) Engineer , your responsibilities… more
    onsemi (11/09/24)
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  • Sr. Physical Design Methodology…

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... trade-offs. Key job responsibilities Define, develop and deploy innovative physical design methodologies (RTL2GDS) and CAD flows...5+ years of experience in developing physical design methodology or CAD flows in synthesis, PNR more
    Amazon (01/16/25)
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  • Senior E/E & Semiconductor Engineer - ASIC…

    Capgemini (San Francisco, CA)
    ** Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San… more
    Capgemini (01/15/25)
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  • Senior ASIC Physical Design

    Capgemini (Santa Clara, CA)
    **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition ID:**… more
    Capgemini (01/15/25)
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  • ASIC STA Engineer

    Cisco (San Jose, CA)
    …and correlation between PNR , Spice, and STA, along with advising the Physical Design team on best practices. * Additionally, you'll develop methodologies, ... and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll be working closely with the… more
    Cisco (11/08/24)
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