- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze ... 10yrs or MS + 7yrs in EE/CS - 5+ years of experience in developing physical design methodology or CAD flows in synthesis, PNR, and sign-off areas for… more
- Qualcomm (Austin, TX)
- …Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer , you will work with ... flows. + Good data analytical skills to identify and root cause physical design issues. **Roles and Responsibilities** + Work with cross functional teams (RTL,… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for multiple design configurations across multiple process nodes. Responsibilities + Develop Quadric… more
- NVIDIA (Santa Clara, CA)
- …devices for high-speed optical interconnect and sensing applications. + Developing physical design methodologies for implementation of graphics processors and ... driving cars. Come join us in our mission to Engineer the next generation of best-in-class products. Our teams...and creative solutions to the state of the art physical design problems that are needed for… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's ... aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical ...out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl,… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: ... Start Date: Right Away Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs; Job Description: As a Sr. physical design engineer , you will contribute to all … more
- Qualcomm (Folsom, CA)
- …to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL ... and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will...out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.… more
- Cadence Design Systems, Inc. (Cary, NC)
- … design . As well as participating in or leading next generation PHY IP physical design , methodology and flow development, the candidate will work closely ... successful tapeouts.Main Job Tasks and Responsibilities: -Participating in or leading next-generation physical design , methodology , and flow development in… more
- Qualcomm (Austin, TX)
- …Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Physical Design Clock Engineer , you will work with ... design , CAD, block level and top level physical design teams to create best in...standard cell optimizations, and clock construction. + Defined clock methodology across various designs. + Preferred experience in deep… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...data-path intensive designs. 23. Experience in the 3D-IC technology, methodology , and advanced packaging. 24. Experience in validating Power… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...data-path intensive designs. 24. Experience in the 3D-IC technology, methodology , and advanced packaging. 25. Experience in validating Power… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...data-path intensive designs. 23. Experience in the 3D-IC technology, methodology , and advanced packaging. 24. Experience in validating Power… more
- Capgemini (San Francisco, CA)
- …**Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design Engineer_ **Location:** _CA-San ... - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level *Understanding...both block and chip level *Understanding constraints and fixing design /timing techniques *Block level implementation from netlist to GDS… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in...of circuits and SPICE, as well as experience in methodology and/or flow development and automation. NVIDIA is widely… more
- Broadcom (San Jose, CA)
- …features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for the ... signal and power EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing with internal and external teams including … more
- Broadcom (San Jose, CA)
- … methodology , power planning and analysis, timing closure, signal integrity and physical design checks. Participate in large complex design ... you apply.** **Job Description:** Broadcom is lookign for ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, … more
- Broadcom (San Jose, CA)
- …Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at ... in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical … more
- Capgemini (San Francisco, CA)
- …** **Job Location:** **San Francisco CA** **Job Description** We are seeking Senior Design Verification Engineer for our Full Time role with Capgemini ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification Engineer_ **Location:** _CA-San Francisco_… more