- Apple (Beaverton, OR)
- …that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ... ERC sign-off for digital and mixed signal designs, drive power ERC sign-off at full-chip level, drive UPF... power sign-off flow more robust and expand power sign-off methodology for next generation mobile… more
- Intel (Phoenix, AZ)
- …Bus fabric, including, but not limited to APB/AHB/AXI Power management with multiple power domains, UPF , Power state tables. Knowledge of lint tools, CDC ... cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced… more
- Apple (Cary, NC)
- …simulations Working experience using LLMs for efficiency and quality Experience with power -aware ( UPF ) or similar verification methodology Excellent ... the game? We have an opportunity for an outstandingly hardworking design verification engineer ! As a member of our wide-ranging group, you will have the rare… more
- Apple (Beaverton, OR)
- …simulations Some working experience using LLMs for efficiency and quality Experience with power -aware ( UPF ) or similar verification methodology Knowledge of ... the game? We have an opportunity for an outstandingly hardworking design verification engineer ! As a member of our wide-ranging group, you will have the rare… more
- Intel (Phoenix, AZ)
- …interaction of computer hardware with software. Experience with Low power / UPF implementation/verification techniques. Experience with Formal verification ... competitive product in the market. WHO YOU ARE: As an IP Logic Design Engineer your responsibilities will include but are not limited to Designing and/or integrating… more
- ManpowerGroup (Phoenix, AZ)
- …Preferred Experience (Nice to Have) Experience with multi-voltage designs and low- power verification ( UPF /CPF). Familiarity with DFM (Design for ... Job Title: Physical Verification Engineer (ASIC Design) Location: USA & Canada (Remote...checks, and final report generation. Collaborate with CAD and methodology teams to refine verification flows and integrate new… more
- Intel (Phoenix, AZ)
- …Bus fabric, including, but not limited to APB/AHB/AXI Power management with multiple power domains, UPF , Power state tables. Knowledge of lint tools, CDC ... cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced… more
- NVIDIA (Santa Clara, CA)
- …in advanced nodes and their impact on DRC closure and PPA optimization + Understanding of power intent files such as UPF , and use of FSDB/SAIFs for power ... of GPU, CPU and SOCs, with emphasis on PPA ( Power , Performance, Area) and runtime improvement of the physical...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
- Meta (Sunnyvale, CA)
- … power grid planning 19. Experience with low power implementation, power gating, multiple voltage rails, UPF /CPF knowledge 20. Experience in planning, ... methodology , and advanced packaging 25. Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC **Public Compensation:**… more
- Microsoft Corporation (Mountain View, CA)
- …to tools Timevision, Fishtail, Formality/LEC, Genus, Fusion Compile. - Expertise in RTL power / UPF linting flows like Power Artist/Jules, VCLP. - Expertise ... curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and… more
- ManpowerGroup (Phoenix, AZ)
- …Experience (Nice to Have)** + Experience with **multi-voltage designs** and **low- power verification** ( UPF /CPF). + Familiarity with **DFM (Design for ... **Job Title: Physical Verification Engineer (ASIC Design)** **Location: USA & Canada (Remote...and final report generation. + Collaborate with CAD and methodology teams to refine verification flows and integrate new… more
- Google (San Diego, CA)
- …simulations. + Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. + Participate in synthesis, timing/ power estimation and ... Senior ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain...Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology . **Preferred qualifications:** + Master's degree or PhD in… more
- Global Foundries (Richardson, TX)
- …the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Summary of ... Role: Seeking a Senior System-on-Chip Design Verification engineer to verify the High-Performance Data Processing Unit Chiplets and Automotive Microcontrollers . The… more
