- Capgemini (Santa Clara, CA)
- …US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _RTL Engineer - RTL Signoff Engineer_ **Location:** _CA-Santa Clara_ ... We at Capgemini engineering are looking for a top-tier RTL Engineer . In this role you will...to run Real Intent tools LINT, CDC and RDC signoff tools. Setup Real Intent tools for RTL… more
- SpaceX (Irvine, CA)
- Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Amazon (San Diego, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer -STA to continue to innovate on behalf of our customers. We are a part of ... history. Roles & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA, Crosstalk… more
- Qualcomm (San Diego, CA)
- …multi-core CPU operations for all Qualcomm Business Units. As a CPU Physical Design Engineer , you will work with microarchitecture and RTL design team to ... smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU)...implementability, area, timing and power. + Synthesize the Verilog RTL into gate level designs and perform optimizations. +… more
- Cisco (San Jose, CA)
- …physical design Team which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities ... primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip...silicon validation phases with additional exposure to physical design signoff activities. What You'll Do You will be part… more
- Cisco (Maynard, MA)
- …with technologies that involve the latest submicron technologies. An ASIC PD engineer would be involved in developing and optimizing physical floorplan and their ... implementation. What You'll Do The Physical Design Engineer Co-op will perform one or more of the...area optimization of design * Static Timing analysis and signoff closure * Physical verification and signoff … more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Cadence Design Systems, Inc. (Austin, TX)
- …to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff ... with 8-10 years industry related experience in design and EDA (Digital Implementation/ Signoff ) + Understands ASIC Design implementation process and steps + Strong… more
- Cadence Design Systems, Inc. (Austin, TX)
- …technology industry. This position is for a synthesis and design engineer . Responsibilities + Develop/improve highly automated and customizable synthesis design ... design method practices to enable better synthesis convergence. + RTL /logic design skills as well as physical design skills...solutions and drive execution. + Run, debug, and fix signoff closure issues in static timing analysis (STA). +… more
- Microsoft Corporation (Mountain View, CA)
- …Intelligence Silicon Engineering team is seeking a **Senior Design Verification Engineer ** to deliver premium-quality designs once considered impossible. We are ... an extremely efficient manner. We are looking for a **Senior Design Verification Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip… more
- ManpowerGroup (Phoenix, AZ)
- **Job Title:** **Physical Design-Power Integrity Flow Development Engineer ** **Location:** + **Primary:** Phoenix, AZ + **Secondary:** Remote in the US. **Experience ... of ASIC SoC design at various design stages, from RTL to gate-level netlist. + Develop and own power...nodes (7nm and below) + Low power implementation and signoff , including power gating, multiple voltage rails, and UPF/CPF… more
- Qualcomm (San Diego, CA)
- …synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL ... design and physical design teams to identify timing requirements and bottlenecks. + Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. + Review and integrate HM constraints into SoC and… more
- ManpowerGroup (Phoenix, AZ)
- **SOC Integration/STA/Synthesis Engineer ** Required Skills: + Develop and own physical design implementation of multi-hierarchy low-power designs including ... best in class in low power and high performance with logically equivalent RTL transforms + Experience with multi-clock and multi-power domain designs. + Proficiency… more