- SpaceX (Irvine, CA)
- Sr. SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING)… more
- SpaceX (Irvine, CA)
- SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... this possible, with the ultimate goal of enabling human life on Mars. SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)… more
- SpaceX (Sunnyvale, CA)
- …flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: + Strong experience in ASIC / SOC RTL2GDSII physical design and signoff flows + Strong ... Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering)...solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis… more
- Capgemini (San Francisco, CA)
- …digital top level and/or blocks, with experience across the complete ASIC / SOC design flow including routing, static timing closure, EM/IR analysis and ... **Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for...knowledge. *Experience in Block-level and Full-chip integration. *Knowledge of signoff closure - Timing with SI and… more
- Amazon (San Diego, CA)
- …advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC ... STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. - Full chip timing constraints development,...and Signoff for a complex, multi-clock, multi-voltage SoC . - Streamlining the timing signoff… more
- Qualcomm (San Diego, CA)
- …and integrate HM constraints into SoC and ensure correlation between HM and SoC timing . + Analyze timing across modes and corners, understand concepts ... for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate...validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. +… more