- NVIDIA (Santa Clara, CA)
- …integral part of the SOC Design team to develop and improve our RTL top - level assembly process and tool set + Top - level assembly: Test new ... The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design...roadmap to address upcoming project challenges for top - level assembly + Create complex GPU, SOC ,… more
- Micron Technology, Inc. (Dallas, TX)
- …the design and development of HBM base die SoC solutions, including top - level design , verification, and integration of various IP blocks. + Ensure ... signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate- level design... top talent to build a world-class HBM SoC design team. + Challenge the team… more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... We are looking for SOC Design Engineer! The complexity of...complex GPU and Tegra chips and interface, directly with unit- level ASIC, Physical Design , CAD, Package … more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... Are you looking for a SOC Design Engineer opportunity? If yes,...complex GPU and Tegra chips and interact directly with unit- level ASIC, Physical Design , CAD, Package … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- General Dynamics Information Technology (Colorado Springs, CO)
- **Req ID:** RQ166630 **Type of Requisition:** Regular **Clearance Level Must Be Able to Obtain:** Top Secret SCI + Polygraph **Public Trust/Other Required:** ... experience **US Citizenship Required:** Yes **Job Description:** **RQ166630 Security Operation Center ( SOC ) Analyst Lead** Lead SOC Analyst's primary function is… more
- SpaceX (Irvine, CA)
- …STA Signoff. + Experience with power intent and upf development for block and soc top . + Familiar with formal verification and implementing functional ecos. + ... Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon... and timing closure + Deep understanding of ASIC design flow, top -down and bottom-up design… more
- Meta (Austin, TX)
- …7+ years of experience as a Digital Design Engineer 10. Experience with top level integration using automation tools. 11. Experience in RTL coding, synthesis ... Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture...and/or SoC Integration. 12. Experience in digital design … more
- Leidos (Arlington, VA)
- …(> GHz) design techniques + ARM or RISC-V embedded processor based SoC design experience + Experience with performance characteristics of analog data ... of Leidos is looking for a FPGA DSP Firmware Design Engineer to work with a multi-disciplined design...integrate DSP applications for latest System on a Chip ( SoC ) implementations such as Xilinx Zynq Ultrascale+, Intel Stratix-10,… more
- Leidos (St. Petersburg, FL)
- …(> 20GHz) design techniques * ARM or RISC-V embedded processor based SoC design experience * Proven experience in the military/aerospace hi reliability ... for a FPGA DSP Firmware Engineer to lead a design team to design , develop, simulate, and...testing. * Conduct experimental tests on latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications… more
- Amazon (Boise, ID)
- …buses like AMBA AXI4 - Experience in integrating third party IP blocks, building top level modules, defining clock domains and power domains - Large breadth ... in consumer devices. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI,...with ARM and various DSP ISA - Experience debugging system- level issues - Experience in entire design … more
- Amazon (Cupertino, CA)
- …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... Engineering or related technical field - 5+ years of experience in RTL design for SOC - 5+ years of experience VLSI engineering - 5+ years of experience… more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. NVIDIA is on the move and ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- ManpowerGroup (Phoenix, AZ)
- …in vector and vector-less modes of ASIC SoC design at various design stages, from RTL to gate- level netlist. + Develop and own power grid implementation ... & implementation + Power integrity analysis at block and top level , including EM, IR & ESD...IR & ESD analysis, and power reduction techniques in SOC design + Power constraints generation and… more
- Actalent (Redmond, WA)
- …to have with PrimePower, PP-RTL/PowerArtist, Power Replay & Empower Skills: UPF, VCLP Top Skills Details: UPF,VCLP Experience Level : Intermediate Level About ... Indicators: Performance will be assessed based on meeting deadlines. Top 3 Hard Skills Required + Years of Experience...1. Minimum 3-5 years Creating UPF files at block, SoC levels & all levels in 2. Minimum 3-5… more
- The Boeing Company (Tukwila, WA)
- …industry Electronic Design Automation (EDA) tools and methodologies for digital ASIC/FPGA/ SoC design and verification + Knowledge of signal processing, image ... Engineer** for a broad range of experience levels including: **Mid- Level , Lead, Senior** . This position will be based...and support verification of these algorithms. **Position Responsibilities:** + Design and execute trade studies for SoC … more
- Cisco (San Jose, CA)
- …issues, provide solutions and ensure signoff clean results * Work with block and top level implementation teams to understand physical aspects and feedback on ... necessary updates * Work closely with block and TOP level physical implementation, IP development teams...with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical … more
- Axiom Space (Webster, TX)
- …+ Interface with external companies to create custom IP cores + Integrate IP cores into top - level FPGA design + Interface with software and PCB designers to ... ensure FPGA design meets system- level requirements + Generate ...design signals interfaces + Working knowledge of Xilinx design /debug tools and SoC (MPSoC or RFSoC)… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …timing closure, power optimization, and physical verification for both of block and Chip top level You will also be responsible for interfacing with the Physical ... of technology. As a core member of the PHY Design team, your responsibilities will span across various aspects...teams in multiple successful ASIC/IP tapeouts. Knowledge of the IP/ SoC level timing closure flow and methodology.… more
- NVIDIA (Santa Clara, CA)
- …HSpice, Finesim, XA) + Experience in crafting test bench environments for component and top level circuit verification + Expertise in System Verilog or similar ... We are looking for an Engineer to verify the design and implementation of the world's leading SoC 's and GPU's. This position offers the opportunity to have real… more