- Meta (Austin, TX)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... (Python, TCL) used to build tools and flows 21. Knowledge of Timing /physical libraries, SRAM Memories. **Public Compensation:** $173,000/year to $249,000/year +… more
- Micron Technology, Inc. (Richardson, TX)
- …Static Timing Analysis for Partition Level and Full Chip Level Timing Closure, SRAM Compilers, Physical Design Verification (DRC/LVS), Formal Equivalence ... to enrich life. As an HBM SOC Physical Design Engineer , you will be responsible for the design &...+ Assisting Front End Design and Integration Engineers with SRAM /RF specification and synthesis design constraints. + Resolving and… more
- SAIC (Eglin AFB, FL)
- …seeking a highly skilled and experienced Mid-Level FPGA (Field Programmable Gate Array) Engineer to join our team. The ideal candidate will have a strong background ... implement memory buffering and caching systems, including DDR3/4, QDR, and SRAM + Develop and implement signal processing algorithms, including filtering,… more
- TEKsystems (Fort Walton Beach, FL)
- …seeking a highly skilled and experienced Mid-Level FPGA (Field Programmable Gate Array) Engineer to join our team. The ideal candidate will have a strong experience ... implement memory buffering and caching systems, including DDR3/4, QDR, and SRAM Develop and implement signal processing algorithms, including filtering, modulation,… more
- Meta (Austin, TX)
- …Physical Design flow such as Floorplanning, CTS, Routing 21. Good Understanding of Timing /physical libraries, SRAM Memories. 22. Knowledge of STA signoff and ... in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for… more
- Meta (Austin, TX)
- …with SOC Design Integration and Front-End Implementation. 17. Knowledge of Timing /physical libraries, SRAM Memories. 18. Experience with Design Compiler, ... in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for… more
- Meta (Austin, TX)
- **Summary:** Meta is seeking an ASIC Engineer to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling ... engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs. + Developing ... properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; +… more