- Qualcomm (Austin, TX)
- …with a shared vision to build products to change the world. As a CPU SRAM Design Engineer , you will design, improve, and analyze digital circuits for memories. ... The role involves full ownership of custom SRAM and RF designs from schematic capture to analysis...simulation and monte carlo analysis. + Experience with static timing analysis. **Preferred Qualifications** + MS degree in Electrical… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior SRAM Engineer ! The Full Custom Macro team at NVIDIA designs specialized RAM implementations for NVIDIAs wide array of processing ... Join a team of dedicated engineers developing the custom SRAM circuits that help power these chips. What you'll...developing and using various flows and methodologies including: Static Timing analysis, EM and IR analysis, Formal Verification At… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior SRAM Engineer within our Full Custom Memory (FCM) team! The FCM team designs specialized RAM implementations across NVIDIAs wide ... generation of AI chips? Join a team of dedicated engineers developing the custom SRAM circuits that help power these chips. What you'll be doing: + Design… more
- Meta (Sunnyvale, CA)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... (Python, TCL) used to build tools and flows 21. Knowledge of Timing /physical libraries, SRAM Memories. **Public Compensation:** $142,000/year to $203,000/year +… more
- Meta (Sunnyvale, CA)
- …Physical Design flow such as Floorplanning, CTS, Routing 22. Good Understanding of Timing /physical libraries, SRAM Memories. 23. Knowledge of STA signoff and ... in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for… more
- Meta (Austin, TX)
- **Summary:** Meta is seeking an ASIC Engineer to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling ... engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design… more
- Broadcom (Irvine, CA)
- …please Sign-In before you apply.** **Job Description:** **Memory Circuit Design Engineer ** We are looking for energetic and passionate memory design engineers ... the physical macro + Integrate characterization flow to extract timing and power information + Develop scripts to automate...+ Working Knowledge of Common memory types such as SRAM , RF, ROM and familiarity with CMOS digital circuits… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs. + Developing ... properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs. + Developing ... properties (FPGA IPs) for Protium platform, including design, verification, integration, timing closure, documentation and releasing the IPs to end users; +… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Principle DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction...+ Memory BIST insertion and verification experience on embedded ( SRAM , CAM, eDRAM, ROM) + Boundary scan Verification and… more
- Qualcomm (San Diego, CA)
- …the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT ... debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected… more