- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Broadcom (Fort Collins, CO)
- …correct on schedule ASIC designs by relying on proven flows and methodology. As a STA Design Automation Engineer you will join a highly skilled team of engineers ... This position would focus on developing, testing, and enhancing our STA methodology and flow. **Qualifications:** + BS Electrical/Computer Engineering +8 years… more
- Ford Motor Company (Dearborn, MI)
- …and more! **In this position ** We are looking for a degreed engineer with prior manufacturing experience and a strong quality background. Key responsibilities will ... senior leaders in the Ford product development, research, purchasing, and site STA teams. This will require excellent verbal and written communication skills and… more
- NVIDIA (Westford, MA)
- …amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class CDC/ STA Design Engineers to join our outstanding Networking Silicon engineering ... (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis ( STA ) constraints and methodology for our DPUs and SOCs...for DPUs and SOCs. + Develop and maintain key CDC/ STA checks and associated sign-offs for DPUs and SOCs.… more
- Cisco (San Jose, CA)
- …and noise, while managing ECO tasks. *Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and ... STA , along with advising the Physical Design team on...*Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $100,100 to… more
- Qualcomm (San Diego, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting… more
- SpaceX (Irvine, CA)
- …computer science + 5+ years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC multimode ... deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer /Senior: $170,000.00 - $230,000.00/per year Your actual level and… more
- SpaceX (Irvine, CA)
- …critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA /Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX... STA /Timing Engineer /Level II: $140,000.00 - $170,000.00/per year Your actual level… more
- Cadence Design Systems, Inc. (Cary, NC)
- …-Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes. -Perform physical design implementation, ... including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. Position Requirements: - Bachelor or above degree in majors… more
- DoorDash (San Francisco, CA)
- …the foundation for decision-making at DoorDash. About the Role DoorDash is looking for a Sta ff Software Engineer ,Data to be a technical lead and help architect ... about you because + 8+ years of professional experience as a hands-on engineer and technical leader leading multiple projects + 6+ years experience working in… more
- Qualcomm (San Diego, CA)
- …different projects and support timing sign off for complex SOC's. Hands on contribution for STA timing sign off. + A timing Engineer should be able to understand ... Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Timing Engineer , you will play a vital role in Timing analysis targeting the… more
- Qualcomm (Folsom, CA)
- …CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing ... One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- Ford Motor Company (Dearborn, MI)
- **In this position ** We are looking for a degreed engineer with prior manufacturing experience and a strong quality background. Ideal candidates for this position ... or experience supporting a supplier manufacturing site as a supplier engineer . Key responsibilities will include performing Casting Process new technology… more
- Meta (Austin, TX)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for RTL-Synthesis and ... PrimeTime- STA for the blocks and the top-level including SOC....Hierarchical Constraints for Functional & DFT Modes. 4. Perform STA for full chip and Physical partition blocks using… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for RTL-Synthesis and ... PrimeTime- STA for the blocks and the top-level including SOC....Hierarchical Constraints for Functional & DFT Modes. 4. Perform STA for full chip and Physical partition blocks using… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...practices. * Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- Meta (Austin, TX)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. 8. Analyze the… more