- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. ... inventiveness and intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for high-performance designs, eg… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
- The Boeing Company (Kent, WA)
- …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers at Lead, Senior & Principal levels to join us… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and … more
- Qualcomm (Santa Clara, CA)
- …Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Science, Engineering, or related field and 1+ year of ASIC design , verification, validation, integration, or related...systems modelling language proficiency is a plus - WIFI Physical layer knowledge is a plus **Principal Duties &… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 -… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the… more
- NVIDIA (Santa Clara, CA)
- …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...SOC clocking. The team collaborates with the front end design team to understand the clocking requirements for the… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
- SpaceX (Irvine, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +...design and timing closure + Deep understanding of ASIC design flow, top-down and bottom-up … more
- NVIDIA (Westford, MA)
- …and circuit designers to deliver best in class IP + partnering with our Physical Design team on partitioning, floorplanning and timing closure + providing ... lower layers of the OSI stack in general + in-depth understanding of physical design + strong working knowledge of Verilog or System Verilog + strong… more
- NVIDIA (Westford, MA)
- …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level,… more
- Micron Technology, Inc. (Minneapolis, MN)
- …validation engineer. Our success depends on close collaboration between Analog and Digital Design , Verification, Physical Design , and Validation engineers to ... develop industry-leading memory solutions. Job requirement: + Excellent problem-solving skills + Fluent in object-oriented Python and C++ programming + Familiar with using source control management (we use git) + Proficiency in Linux/Unix environment +… more
- Amazon (Portland, OR)
- …generation of ML accelerator at edge. Work hard. Have fun. Make history. As a Senior Physical Design Engineer, you will: - Work with RTL/logic designers ... Teams Basic Qualifications - BS in EE/CS - 7+ years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm -… more
- GrammaTech, Inc. (MD)
- …with RoT techniques including TPM + Experience with firmware-level code + FPGA physical design + Experience with device characterization or PUF techniques + ... with the other engineering personnel to coordinate the interrelated design and assure project completion + Applies ASIC...physical designers to successfully complete their specific P&R design tasks + Work with tool and library vendors… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for the ... network and last-level caches , working closely with the physical design team on implementation, synthesis and...expertise is required as is a deep understanding of ASIC design flow including RTL design… more