- Cisco (San Jose, CA)
- …and noise, while managing ECO tasks. *Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and ... STA , along with advising the Physical Design team on...*Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- SpaceX (Irvine, CA)
- …critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: +… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Northrop Grumman (Baltimore, MD)
- …to join our team as a Principal Digital Engineer / Senior Principal Digital Engineer (FPGA and ASIC Design) based out of Linthicum, MD. **What You'll get ... team in Mission Systems that encompasses Digital Engineering to support FPGA and ASIC product development. + Work closely with design engineers and will utilize your… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling… more
- Google (Mountain View, CA)
- …ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon ... a must. The Role: We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have… more
- L3Harris (Camden, NJ)
- Job Title: Senior Electrical Engineer (FPGA Design) Job Code: 19447 Job Location: Camden, NJ Schedule: 9/80 Regular with every other Friday off Job Description: ... Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff...Synthesis, Place and Route (PAR) and Static Timing Analysis ( STA ) + Perform RTL quality using: Lint, Reset Domain… more
- NVIDIA (Santa Clara, CA)
- …industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams with advanced implementation ... experience; MS preferred + Be familiar with Verilog and ASIC design along with experience in commercial EDA tools... methodologies such as RTL Lint, CDC, DFT or STA . + Experience with compute farm interaction: software deployment,… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC project ... + Conformal LEC (Priority #1) + Synthesis tools (Synposys & Cadence) + Timing/ STA tools (PrimetimeSI & Cadence tools). **Life at Capgemini** Capgemini supports all… more
- Broadcom (Irvine, CA)
- …**Job Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? ... a resident expert in areas such as physical design, STA , DFT, and packaging? Have you taped out so...range of products that keep the globe connected. Our ASIC products division is looking for senior ,… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... we're building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind, code reviews.… more
- Micron Technology, Inc. (Atlanta, GA)
- …technology and growing upon your imagination and creativity. As a Principal RTL Design Engineer , you will be responsible for all aspects of DRAM digital IP design, ... **_or Principal_** **_Engineer_** **What's Encouraged Daily:** + As a senior member of the DRAM design engineering team, you...will be responsible for designing DRAM digital IPs with ASIC flows. You will implement, document and deliver high… more
- RTX Corporation (Sacramento, CA)
- …Job Summary: An exciting opportunity exists at Raytheon for a Principal Digital IC Design Engineer to join our strong team. In this position you will be part of a ... part of this team, you will be participating in mixed-signal ASIC /ROIC development activities with cross-functional teams including chip architecture, specification,… more