• Senior ASIC Timing

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
    NVIDIA (09/20/24)
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  • Senior ASIC Timing

    NVIDIA (Westford, MA)
    …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at...from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and… more
    NVIDIA (11/14/24)
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  • Sr. SOC/ ASIC Timing Signoff…

    SpaceX (Irvine, CA)
    Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... enabling human life on Mars. SR. SOC/ ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
    SpaceX (11/22/24)
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  • ASIC and/or FPGA Design & Verification…

    The Boeing Company (Kent, WA)
    …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will lead ... & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers at Lead,... and/or FPGA Design and Verification Engineers at Lead, Senior & Principal levels to join us as part… more
    The Boeing Company (11/16/24)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (San Francisco, CA)
    **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... of complex digital top level and/or blocks, with experience across the complete ASIC /SOC design flow including routing, static timing closure, EM/IR analysis and… more
    Capgemini (10/16/24)
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  • Senior ASIC Floorplan Design…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
    NVIDIA (11/06/24)
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  • Senior ASIC Physical Design…

    Capgemini (San Francisco, CA)
    **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... partitioning, timing budget generation, power planning, top-level PnR, CTS, block...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
    Capgemini (10/16/24)
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  • Senior ASIC Design Engineer

    Cisco (San Jose, CA)
    …provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography ... breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact * Write micro-architecture...participate in reviews. * Implement Verilog RTL to meet timing , performance, and power requirements. * Contribute to full… more
    Cisco (11/19/24)
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  • Senior ASIC Design Engineer

    NVIDIA (WA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
    NVIDIA (11/10/24)
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  • Senior Principal Digital Engineer

    Northrop Grumman (Baltimore, MD)
    …to join our team as a Principal Digital Engineer / Senior Principal Digital Engineer (FPGA and ASIC Design) based out of Linthicum, MD. **What You'll get ... team in Mission Systems that encompasses Digital Engineering to support FPGA and ASIC product development. + Work closely with design engineers and will utilize your… more
    Northrop Grumman (09/20/24)
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  • Senior ASIC Design Engineer

    Tarana Wireless (Milpitas, CA)
    This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
    Tarana Wireless (11/02/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... fully verified design by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure… more
    NVIDIA (11/05/24)
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  • Senior ASIC Physical Design…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as dataflow and exhibiting… more
    NVIDIA (09/27/24)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
    SpaceX (11/15/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to have real ... to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/ timing clean design. + Support post-silicon validation activities. + Work with… more
    NVIDIA (10/08/24)
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  • Senior ASIC Physical Design…

    NVIDIA (Santa Clara, CA)
    …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... checks, etc. + Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and… more
    NVIDIA (09/25/24)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers ... BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD)...+ You have experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing more
    NVIDIA (11/13/24)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $160,000.00 - $220,000.00/per year Your ... Sr. ASIC Design Engineer (Silicon Engineering) at...Sr. ASIC Design Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing more
    SpaceX (11/16/24)
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  • ASIC /Rtl Design Engineer

    US Tech Solutions (San Jose, CA)
    …portions of the design and implementation of blocks to meet functional, timing , area, and power requirements. * Collaborate with architecture and hardware teams ... years' experience * Must have proven track record of ASIC design on several production tape-outs. * Experience in...APB, AXI, CHI protocols. * Experience with synthesis, static timing analysis & optimizations. * Experience with design involving… more
    US Tech Solutions (11/22/24)
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  • ASIC Digital Design Engineer - WiFi…

    Qualcomm (San Jose, CA)
    …to help create a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design, optimize, verify, validate, implement, ... degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree… more
    Qualcomm (09/23/24)
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