- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... Be Doing: + Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on… more
- Google (Mountain View, CA)
- …steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, STA , timing closure, EM-IR, PV, CDC analysis, LEC etc. ... can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development...design flows and methodologies including synthesis, place and route, STA , Formal Verification, CDC and Power Analysis… more
- Capgemini (San Francisco, CA)
- **Job Title: RTL Engineer ** **Job Location:** **San Francisco CA** **Job Description** We are seeking Digital Design/RTL Design engineer for our Full Time ... and evolving specifications. + Perform RTL coding, Lint checks, CDC tests, crafting timing constraint file, and work closely...crafting timing constraint file, and work closely with Synthesis, STA , PD and DFT teams to meet all functional… more
- Capgemini (Santa Clara, CA)
- …get introduced which including DFT structures. + Carry out static checks including Lint/ CDC (Spyglass), synthesis, LEC and STA . Debugging and fixing functional ... **Job Role: RTL Engineer ** **Job Location: Santa Clara CA** **Job description:**...code for IP development/RTL integration, checking the code for Lint/ CDC issues, checking synthesizability and timing quality of the… more
- Northrop Grumman (Baltimore, MD)
- …your career. We are looking for you to join our team as a Principal Digital Engineer / Senior Principal Digital Engineer (FPGA and ASIC Design) based out of ... industry standard ASIC front-end design tools for synthesis, LEC, CDC + Experience with STA constraints generation and timing closure + Experience with MATLAB,… more
- L3Harris (Camden, NJ)
- Job Title: Senior Electrical Engineer (FPGA Design) Job Code: 19447 Job Location: Camden, NJ Schedule: 9/80 Regular with every other Friday off Job Description: ... Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of… more
- NVIDIA (Santa Clara, CA)
- …Machine Learning/Deep Learning + Experience in other ASIC methodologies such as RTL Lint, CDC , DFT or STA . + Experience with compute farm interaction: software ... deployment, performance optimization, containers, etc. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working… more
- Micron Technology, Inc. (Atlanta, GA)
- …Verilog and simulation tools + Understand ASIC low power design techniques + Knowledge of CDC , RDC, STA and UPF + Experience in RTL development for logic or ... your imagination and creativity. As a Principal RTL Design Engineer , you will be responsible for all aspects of...digital IP design, from specification, RTL, verification, synthesis, lint, CDC , LEC, and static timing analysis to deliver a… more