- NVIDIA (Santa Clara, CA)
- …imagination and intelligence. Make the choice to join us today. DFX Methodology Group at NVIDIA works on groundbreaking innovations involving crafting creative ... 3+, or PhD with 2+ years of experience in DFT , system architecture, or RTL design. + Understanding of...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
- Cisco (San Jose, CA)
- …flows, and post-silicon test bring up procedures. Preferred qualifications: * DFT CAD development - Test Architecture, Methodology and Infrastructure ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior DFT Engineer to join our dynamic and growing team! If you ... + You will be responsible for all aspects of testing including methodology , logic insertion, verification, test pattern generation, test program bring-up, and… more
- NVIDIA (Santa Clara, CA)
- …to join us today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In ... significantly. Modern clocking design needs to balance high frequency clocks with power, DFT , noise, circuit and physical design constraints. What you'll be doing: +… more
- Amazon (Cupertino, CA)
- …integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, ... flows for ML Accelerator chips in advanced nodes Drive improvement in RTL2GDS flows/ methodology for PPA and TAT improvements Create Dashboard and Central reports for… more
- Microsoft Corporation (Hillsboro, OR)
- …+ Perform cross-functional decision making across UPF (Unified Power Format)/Low Power methodology /architecture, DFT methodology , Synthesis, Place and Route ... Artificial Intelligence and Computing. We are looking for a ** Senior Silicon Engineer ** to join our team!...end-users. + Excellent Communication skills across the board + DFT methodology and handling DFT … more
- Micron Technology, Inc. (Atlanta, GA)
- …how the world uses information to enrich life. Micron is searching for its next Principal/ Senior Design Verification Engineer ! In this role, you will work with a ... and process improvements; including the effort to port-over the probe and burn DFT patterns into the verification flow. + Provide verification support to the DRAM… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS...GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing… more
- Belcan (Austin, TX)
- Senior Electronics Test Engineer I Job Number: 353143 Category: Electrical / Electronics Description: Job Title: Senior Electronics Test Engineer I ... and test systems, including equipment selection, test fixtures, data logging methodology , and interfaces. * Designing and executing tests at the prototype,… more
- The Boeing Company (Huntington Beach, CA)
- …of these projects. We are seeking a **Digital Integrated Circuit Design Engineer (Mid-Level, Senior or Lead)** with experience developing complex, ... of 3rd party IP (digital, mixed-signal), synthesis, place & route, design-for-test ( DFT ) insertion + Static timing analysis / timing closure + Power analysis,… more
- Microsoft Corporation (Austin, TX)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial ... intent. + Interface with architecture, physical design (PD), design for test ( DFT ), and other teams to optimize tradeoffs within the design. + Provide… more
- Celestica (Richardson, TX)
- …Region: Americas Country: United States State/Province: Texas City: Richardson **Summary** The Senior Reliability Engineer , works in cross functional teams with ... team and seek opportunities to develop new/improve existing durability test methodology to enhance product development efficiency. + Apply problem-solving and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation SoC solutions. We are looking for special individuals with passion and ... and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post silicon… more
- NVIDIA (Santa Clara, CA)
- We are looking to hire a Senior Board Test Engineer who will work in the Test Solutions Group at NVIDIA developing manufacturing GPU/CPU test solutions for Data ... + Investigate and introduce new manufacturing test technology and methodology to improve production efficiency. + Contribute to our...and validation infrastructure. + Review and provide feedback for DFT in the early design stages. + Debug complex… more
- Google (Sunnyvale, CA)
- …OrCAD, Concept, Allegro. + Experience working with PCB design tools and methodology . Preferred qualifications: + Master's or PhD degree in Electrical Engineering, ... Proficiency with high-speed board design/layout. As a PCB Layout Engineer designer on the Platforms Infrastructure team, you will...use correct impedance rules, DFM and Design for Test ( DFT ) rule sets. + Work with hardware engineers, PCB… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want to challenge ... clock distribution and planning as well as impact of DFT logic in timing convergence. + Knowledge of circuits...of circuits and SPICE, as well as experience in methodology and/or flow development and automation. NVIDIA is widely… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with compute farm interaction: software deployment, performance… more
- SpaceX (Irvine, CA)
- …as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint generation and… more
- Amazon (Sunnyvale, CA)
- …and underserved communities around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of the… more
- Micron Technology, Inc. (Folsom, CA)
- …information to enrich life. We are looking for a HBM High-speed IO Design Engineer . Are you passionate about crafting circuits for the next generation of memory that ... RTL-style logic design, custom high-speed PHY design, analog circuit design, and DFT circuits to deliver advanced HBM products using in-house and external foundry… more