- NVIDIA (Santa Clara, CA)
- …innovative CAD Software Developer with particular interest in algorithms for gate-level timing and physical optimization, including sizing and buffering, clock ... + Strength in both CAD software and VLSI design + Strong understanding of VLSI timing ...VLSI design + Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect… more
- NVIDIA (Westford, MA)
- …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... in a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block… more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the ... human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive...most sophisticated strategies of signing off timing in design for world-class silicon performance.… more
- SpaceX (Irvine, CA)
- …and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to achieve ... with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure + Deep understanding of… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- Lasers and Timing Systems Engineering Department Head Job ID 6025 Location SLAC - Menlo Park, CA Full-Time Regular **SLAC Job Postings** **Position Overview** The ... Accelerator Laboratory seeks a mechanical engineer to lead the Lasers and Timing Systems Engineering Department. LCLS is an X-ray Free Electron (FEL) facility… more
- NVIDIA (Santa Clara, CA)
- …GPUs. + Explore design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as ... intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic... design and implementation. + Hands-on experience in physical synthesis, floor planning, P&R, and timing … more
- NVIDIA (Santa Clara, CA)
- …MTBF analysis, logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our...understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure. + Experience in… more
- NVIDIA (Santa Clara, CA)
- …life's work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing from netlist to gds. + Partner with ... design . + Experienced in Synopsys or Cadence place and route, physical design and timing tools. + Ability to form methodologies and automate flows.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...+ Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop… more
- NVIDIA (Santa Clara, CA)
- …interconnect network and last-level caches , working closely with the physical design team on implementation, synthesis and timing closure as well as working ... a liaison between Logic design and Physical design teams responsible for achieving timing , area, performance and power goals of the unit. + Help define… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding ... be doing: + You will lead all aspects of physical design and implementation of SOC devices...- synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical… more
- NVIDIA (Santa Clara, CA)
- …and Verification. + Strong background with hierarchical design approach, top-down design , budgeting, timing and physical convergence. + Familiar with ... strengths today! What you will be doing: + Developing physical design methodologies for implementation of graphics...floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and… more
- NVIDIA (Santa Clara, CA)
- …meet performance, timing and power targets. + Deliver a synthesis/ timing clean design while working with the physical design team ensuring a routable ... We are looking for a Senior CPU Design Engineer! NVIDIA is...with architects, design engineers, verification engineers, and physical design engineers teams to accomplish your… more
- NVIDIA (Santa Clara, CA)
- … by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure a ... NVIDIA is seeking an outstanding Senior ASIC Design Engineer to ...+ Collaborate with architects, verification engineers, software engineers, and physical design engineers to accomplish your goals.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...analysis on the design . + Drive the design and physical implementation of digital and/or… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly… more
- Northrop Grumman (San Diego, CA)
- …the Electronic Design Automation (EDA) Tool Quartus. + Knowledgeable in FPGA physical constraints and achieving timing closure. + Experience with board or ... history, they're making history. Explore a career engineering what's possible as a Digital Design Engineer in San Diego, CA. **What You'll Get to Do:** Our Advanced… more
- Micron Technology, Inc. (Boise, ID)
- …leader in memory and storage solutions, is seeking a highly skilled and motivated Senior /Principal DRAM Design Engineer to join our innovative team in Boise, ID. ... information into intelligence and inspiring advancements that enrich lives worldwide. As a Senior or Principal Lead DRAM Design Engineer, you will play a… more
- NVIDIA (Westford, MA)
- …designers to deliver best in class IP + partnering with our Physical Design team on partitioning, floorplanning and timing closure + providing design ... logic or lower layers of the OSI stack in general + in-depth understanding of physical design + strong working knowledge of Verilog or System Verilog + strong… more
- SpaceX (Sunnyvale, CA)
- …work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at...(eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop,… more