• Senior RTL Analysis

    NVIDIA (Santa Clara, CA)
    …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
    NVIDIA (11/16/24)
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  • Senior Design for Debug Architect…

    NVIDIA (Santa Clara, CA)
    …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
    NVIDIA (09/12/24)
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  • Senior Silicon Engineer PD CAD Signoff

    Microsoft Corporation (Raleigh, NC)
    …+ Establish Logical Equivalence Checking (LEC)/Formal Equivalence Verification (FEV) methodology for hierarchical and block-level partitions between RTL , ... Artificial Intelligence and Computing. We are looking for a ** Senior Silicon Engineer** to join our team! If you...CAD (Computer Aided Design) flow systems + Perform detailed debug/ analysis to guide the RTL and physical… more
    Microsoft Corporation (11/20/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis , methodology alignment, and program execution to ensure pre-silicon and ... NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve...of external and internal IPs. + Contribute to cross-team RTL methodologies to achieve efficient design reuse. + Evaluate… more
    NVIDIA (11/15/24)
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  • Digital Integrated Circuit Design Engineer…

    The Boeing Company (Huntington Beach, CA)
    …SiGe. SSED uses external wafer fabrication but performs design (architecture, RTL , synthesis, circuits, physical design, verification, packaging and test) in house. ... We are seeking a **Digital Integrated Circuit Design Engineer (Mid-Level, Senior or Lead)** with experience developing complex, high-performance ASICs, FPGAs, and… more
    The Boeing Company (11/16/24)
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  • Sr. SOC/ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint generation and… more
    SpaceX (11/22/24)
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  • Senior ASIC Design Engineer

    Cisco (San Jose, CA)
    …and power requirements. * Contribute to full chip integration and timing methodology / analysis . * Develop and analyze functional coverage. * Help define, ... evolve, and support our design methodology . * Collaborate with the verification team to address design bugs and close code coverage. * Work closely with the physical… more
    Cisco (11/19/24)
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  • Senior Synthesis Flow CAD Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
    NVIDIA (11/02/24)
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  • Senior E/E & Semiconductor Engineer - ASIC…

    Capgemini (San Francisco, CA)
    …of the physical chip development, executing from the inception of the design ( RTL or gate netlist) through the tape-out release to wafer fabrication using the ... complete ASIC/SOC design flow including routing, static timing closure, EM/IR analysis and chip finishing.** **Job Responsibility:** *Chip level floor planning,… more
    Capgemini (10/16/24)
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  • Sr. Staff Design Engineer (Low Power)

    Qualcomm (Santa Clara, CA)
    …IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and ... their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon… more
    Qualcomm (10/10/24)
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  • Sr./Principal HBM CAD Engineer - TPG

    Micron Technology, Inc. (Richardson, TX)
    …difficult problems solved and turn customers' dreams into reality faster. The Senior /Principal HBM CAD Engineer is a technical leadership role within the Engineering ... functional & timing verification of cell-based designs (dynamic simulation and static analysis ). Our ideal candidates combine pure digital RTL2GDS blocks with custom… more
    Micron Technology, Inc. (11/21/24)
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  • Principal IO Design Engineer, HBM Design

    Micron Technology, Inc. (Folsom, CA)
    …for AMS design, Advanced CMOS and FinFET technologies. + Understanding of Mismatch analysis & Monte-Carlo methodology /sims, transistor level Circuit level noise ... like ML (Machine Learning) and AI (Artificial Intelligence). HBM incorporates RTL -style logic design, custom high-speed PHY design, analog circuit design, and… more
    Micron Technology, Inc. (10/23/24)
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