- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- Micron Technology, Inc. (Atlanta, GA)
- …flow and DFT verification. + Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis . + Familiarity with ... the world uses information to enrich life. Micron is searching for its next Principal/ Senior Design Verification Engineer! In this role, you will work with a highly… more
- NVIDIA (Santa Clara, CA)
- …Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis , methodology alignment, and program execution to ensure pre-silicon and ... NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve...of external and internal IPs. + Contribute to cross-team RTL methodologies to achieve efficient design reuse. + Evaluate… more
- Northrop Grumman (Linthicum, MD)
- …UVM + Experience developing testplans, participating in reviews, test development and RTL debug ** Senior Principal Engineer Basic Qualifications:** + Bachelor's ... for you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification Engineer based out of Linthicum, MD or Morrisville,… more
- BAE Systems (San Jose, CA)
- …start up with the stability of a large company. We are looking for a senior level chip designer who has strong proficiency in both + ASIC design- performing ... architecture design, RTL coding/simulation, timing closure at layout phase + Verification-...+ Verification- executing testbench creation, functional coverage, test failures analysis , regression Detail requirements + Front End Design and… more
- NVIDIA (Santa Clara, CA)
- …reduce power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, ASIC Design ... for building energy models that integrate into architectural simulators, RTL simulation, emulation and silicon platforms. Key responsibilities include developing… more
- SpaceX (Irvine, CA)
- …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint generation and… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- Teradyne (Tualatin, OR)
- …team working in an exciting, focused atmosphere. We are looking for a Senior FPGA Design Engineer with outstanding technical and leadership skills. The candidate ... Skills + Experience with Digital Design and Architecture + RTL coding, synthesis, timing closure and lab validation +...closure and lab validation + Experience with Static Timing Analysis of ASICs or FPGAs + Experience with digital… more
- Siemens Digital Industries Software (Wilsonville, OR)
- …+ Working knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... chip, board and system design. **Job Overview** Siemens EDA is seeking a senior level, self-starting, motivated, and high performing individual for an opportunity to… more
- Micron Technology, Inc. (Folsom, CA)
- …for AMS design, Advanced CMOS and FinFET technologies. + Understanding of Mismatch analysis & Monte-Carlo methodology /sims, transistor level Circuit level noise ... like ML (Machine Learning) and AI (Artificial Intelligence). HBM incorporates RTL -style logic design, custom high-speed PHY design, analog circuit design, and… more