- Cisco (Maynard, MA)
- …working in a smaller ASIC team can provide. Your Impact As a Physical Design Engineer , you will play a key role in the full RTL-to-GDSII implementation flow for ... advanced semiconductor nodes. You will optimize floor planning and timing , analyze and improve backend design flows, and collaborate across teams to ensure the… more
- The Boeing Company (St. Louis, MO)
- …position is hiring for multiple levels including; Associate Level, Experienced Level, and Senior Level. This role is looking to hire software engineers capable of ... Integration / Continuous Deployment (CI/CD) software build pipeline using an agile methodology focused on code quality, security and automation. Key Capability areas… more
- Hawaiian Electric (Honolulu, HI)
- Wildfire Mitigation Planning Engineer / Senior Wildfire Mitigation Planning Engineer - Oahu Date:Nov 25, 2025 Location: Honolulu, Hawaii (HI), US, 96813 ... seeks to fill at either the Wildfire Mitigation Planning Engineer or Senior Wildfire Mitigation Planning ...on the ongoing development of the WSS. + Develops methodology to apply risk-informed analysis to ensure cost-effective risk… more
- Broadcom (Fort Collins, CO)
- …verification. Contribute to design flow improvements, automation, and deep sub-micron methodology development. Assist in timing analysis, power planning, IR/EM ... exposure to advanced design methodologies and close collaboration with senior engineers across multiple disciplines to deliver industry-leading silicon solutions.… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... an ideal role. What You'll Be Doing: + Develop Timing sign-off flows, constraints and QOR metrics for custom...using standard cells and custom designs. + Validating the timing of custom circuit design using NanoTime and various… more
- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer , Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, ... ensure successful timing closure. + Participate in both static timing analysis methodology development and support, as well as chip implementation and … more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. NVIDIA's ASIC-PD Methodology organization is driving the next generation of AI-assisted timing ... closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead end-to-end solution development - spanning data generation, model… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... with multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Custom Timing Engineer to join our dynamic and growing Circuit Solutions Group! If you are looking for a ... performance and reliability of Nvidia's next generation products. + Develop timing models and methodology for custom macro design at transistor level along with… more
- NVIDIA (Santa Clara, CA)
- …how you can make a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our ... equivalent experience + 6+ years of experience in VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills in… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...methods and techniques + Strong background in STA, extraction, timing and RC correlation + Good understanding of design… more
- NVIDIA (Santa Clara, CA)
- …complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is ... equivalent. + Strong fundamentals in digital design, system and microarchitecture, timing , clocking, power, noise, and control systems; Deep understanding of… more
- NVIDIA (Santa Clara, CA)
- …+ Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Strong understanding of physical design implementation ... eg: physical synthesis, placement, routing, logic restructuring, etc. + Should be a power user of synthesis and/or place and route EDA tools from Synopsys (DC/FC), Cadence (Genus/Innovus) + Good debugging and problem-solving skills + Strong interpersonal… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient ... from concept to first customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- GE HealthCare (Waukesha, WI)
- **Job Description Summary** The Senior Reliability engineer will be an integral part of the central DFR (Design for Reliability) program team within the STO org ... support the development and deployment of the standard GEHC DFR methodology applying relevant reliability concepts, processes, standards, and tools. Activities… more
- RTX Corporation (Cedar Rapids, IA)
- …position is for a highly experienced, highly motivated Electrical or Computer Engineer that will be involved in the design, implementation, verification and ... of high-performance ASICs, FPGAs, and SoPCs for Collins Avionics solutions. As an engineer in this organization, you will be employing best practice design and… more
