- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... an ideal role. What You'll Be Doing: + Develop Timing sign-off flows, constraints and QOR metrics for custom...using standard cells and custom designs. + Validating the timing of custom circuit design using NanoTime and various… more
- SpaceX (Irvine, CA)
- Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are ... Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Should be a power...the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across ... + Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence. + Familiar with various process related design… more
- Renesas (Austin, TX)
- Senior Principal Electrical Engineer Job Description The Performance Computing Power (PCP) group is seeking an experienced Digital IC Designer to join our ... Design:** Lead and oversee digital RTL design, ensuring compliance with timing , area, power, and relevant standards specifications. + **Design Flow Participation:**… more
- Microsoft Corporation (Redmond, WA)
- …** Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer ** to work as digital Application Specific Integrated Circuit (ASIC) ... for ** Senior Quantum Digital Application-Specific Integrated Circuit (ASIC) Design Engineer ** who is as passionate about their own contribution as they are… more
- BAE Systems (San Jose, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Senior Principal Front End ASIC Design Engineer (Hybrid)** **105684BR** EEO ... of a large company. We are looking for a senior level chip designer who has strong proficiency in...both + ASIC design- performing architecture design, RTL coding/simulation, timing closure at layout phase + Verification- executing testbench… more
- Teradyne (Tualatin, OR)
- …team working in an exciting, focused atmosphere. We are looking for a Senior FPGA Design Engineer with outstanding technical and leadership skills. The ... & Skills + Experience with Digital Design and Architecture + RTL coding, synthesis, timing closure and lab validation + Experience with Static Timing Analysis of… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal Integrity Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI model correlations using lab measurements to improve modelling tool/ methodology . + Package substrate and board layout SI design...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- DuPont (Circleville, OH)
- …communities in which we work and live. The Kapton(R) team is seeking a ** Senior Process Engineer ** at the **Circleville, Ohio** facility-30 miles south of ... manufacturing asset at the Circleville site, as well. The ** Senior Process Engineer ** role will work to...complex issues. + Utilizes Lean Manufacturing & Six Sigma methodology . + Responsible to ensure adequate basic data is… more
- IDEX (Oklahoma City, OK)
- …around the globe, chances are, we have something special for you. The Senior Electrical Engineer plays a pivotal role in leading the development ... and procedures for releasing new products to manufacturing. The Senior Electrical Engineer will work both independently...Conduct BOM cost analysis. + Develop and maintain project timing plans. + Lead and support product design reviews.… more
- Northrop Grumman (Annapolis Junction, MD)
- …best work of your career. We are looking for you to join our team as a Senior Software Engineer based out of Annapolis Junction, MD. **What You'll get to Do:** ... The Senior Software Engineer develops, maintains, and enhances...Design or implement complex algorithms requiring adherence to strict timing , system resource, or interface constraints; Perform quality control… more
- DuPont (Newark, DE)
- …Semiconductor Technologies business, has an exciting and challenging opportunity for a Senior Product Engineer (PQE)/ in the Chemical Mechanical Planarization ... technical quality by partnering with product development group on the stage gate methodology + Training field service engineers and other sales staff as required on… more
- Microsoft Corporation (Redmond, WA)
- …future of gaming! Our Electrical Engineering and Firmware team is seeking a Senior Electrical Engineer to lead High Speed Signal design, architecture definition, ... processes. The candidate needs to have an understanding of circuit design, timing analysis, operation, power, performance, in addition to experience in Peripheral… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation SoC solutions. We are looking for special individuals with passion and ... with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to… more
- Micron Technology, Inc. (Boise, ID)
- …the world uses information to enrich life! As a DRAM Technology Reliability Test Engineer , you will be responsible for developing test programs for use in the ... Develop characterization patterns to accurately measure changes in operating current, timing , or functionality brought out by degradation. + Use existing… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... + Experience in succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is leading the way in groundbreaking developments in… more
- Amazon (Sunnyvale, CA)
- …and underserved communities around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of the… more