- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the ... a "learning machine" that constantly evolves by adapting to new opportunities that are hard to resolve, that only...for sign-off. + Knowledge of extraction, device physics, STA methodology and EDA tools limitations. + Shown understanding of… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're...resolution + Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability, methodology … more
- Amazon (Cupertino, CA)
- …emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ... TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability. Fine tune cloud...7yrs in EE/CS - 5+ years developing physical design methodology or CAD flows in synthesis, PNR, and sign-off… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... low cost. You'll provide leadership in the application of new technologies to large scale deployments in a continuous...- You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Perform methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services. + Create and conduct ... on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job...on ASIC/IC design experience who is looking for a new challenge in an absorbing customer facing role. This… more
- Cadence Design Systems, Inc. (Austin, TX)
- …doing challenging designs at advanced nodes and help them with design implementation and signoff . Will serve as the technical expert on Cadence tools as well as a ... required; 5+ years of Digital Design experience in Power Signoff and Physical Implementation of designs at 20nm and...+ Must have experience with digital Place and Route methodology , static timing analysis and at least one scripting… more
- Microsoft Corporation (Mountain View, CA)
- …mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality ... to Microsoft cloud hardware. We are looking for a Senior Design Verification Engineer for customer focused solutions, insight and industry knowledge to envision and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …make an impact on the world of technology. Job Title: Sr Application Engineer (f/m/d) Location: Stockholm (Kista), Sweden Reports to: AE Group Director Job Overview: ... The Cadence Application Engineer (AE) role is a great opportunity to employ...and product development teams supporting Cadence's Custom IC and Signoff software products including: + Virtuoso Schematic Editor +… more
- NVIDIA (Santa Clara, CA)
- …impact on the world! We are currently looking for a Sr VLSI Physical Verification Methodology Engineer . What you'll be doing: + Responsible for support and debug ... methodologies to improve workflow efficiency and timely issue detection. Integrate new workflows and checks into larger workflow automation systems. + Participate… more
- Broadcom (Fort Collins, CO)
- …1 GHz, from concept through production. **Role Overview** This Floorplanning Engineer role focuses on chip-level physical architecture and integration for advanced ... block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff -quality results. + Contribute to design flow automation and methodology … more
- Cadence Design Systems, Inc. (Irvine, CA)
- …signoff ) and/or experience with functional and formal verification tools/ methodology , VIP. Understanding of semiconductor manufacturing eco-systems. * Deep ... required. * Min. 7 years in sales and account management or as a Applications Engineer or Design Engineer with proven track record of success * Deep… more