- SpaceX (Sunnyvale, CA)
- Sr. SOC /ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON ENGINEERING)...and run times + Create integrated hierarchical physical design flow to enable SoC collateral management for… more
- Meta (Sunnyvale, CA)
- …drive execution 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power and higher performance trade-offs 4. ... methodology , and advanced packaging 25. Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC **Public Compensation:**… more
- SpaceX (Sunnyvale, CA)
- …the performance and capabilities of the Starlink network. RESPONSIBILITIES: + Perform SOC top level physical design; floor-planning, I/O, bump & RDL (redistribution ... layer) planning, hard IP integration, partitioning, power /ground grid generation, pin assignment, partition hardening, chip level clock, feedthrough, special… more
- Google (Sunnyvale, CA)
- …+ Ability to deliver on-time STA sign-off and chip delivery including STA flow / methodology , STA flow ownership, timing constraint validation, and timing ... including project planning, scheduling, task allocation, and progress tracking for SOC projects. + Experience in the analysis and cross-chip clock distribution… more
- Intel Corporation (Hillsboro, OR)
- …a wide variety of issues up to and including design and tool/ flow / methodology issues used for layout design. Additional responsibilities: + Designs, ... tools, flow , and methodologies to improve efficiency and optimize power and performance. + Supports development and enhancement of platforms, databases, scripts,… more
- Google (Sunnyvale, CA)
- …Experience leading one or more aspects of physical design or physical design flow / methodology , to successful tape-outs and shipping silicon. + Experience in ... part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products… more
- Broadcom (Broomfield, CO)
- …optimization. + Implement timing and functional ECOs. + Apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for ... position. + Proficient in design implementation activities both at block and SoC level. + Well experienced in floor-planning, partitioning, placement, clock tree… more
- Broadcom (Broomfield, CO)
- …functional ECOs. In this role, the candidate will apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for ... desired PPA metrics. Candidate would also be required to do equivalence checks, STA, Timing closure and power optimization. Should be able to implement timing and… more
- Meta (Sunnyvale, CA)
- …PrimeTime 21. 6. Working with cross-functional teams to support and debug timing, area, and power issues and 22. 7. Flow Automation with TCL, Python, or Perl ... techniques and generate optimized gate level netlist for Timing, Area, and Power . 2. Debug timing/area/congestion issues and resolve w/ RTL & physical designers.… more
- Broadcom (Fort Collins, CO)
- …and IR/EM analysis to achieve signoff-quality results. + Contribute to design flow automation and methodology development for advanced process technologies. ... Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.… more
- Broadcom (Fort Collins, CO)
- …+ Contribute to design flow improvements, automation, and deep sub-micron methodology development. + Assist in timing analysis, power planning, IR/EM checks, ... Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.… more