• SoC Silicon Top

    Google (Sunnyvale, CA)
    SoC Silicon Top - Level Floorplan Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced** Experience owning outcomes and decision making, ... + Own the planning, creation, and delivery of top - level floorplan deliverables and implementation for Silicon SOC projects from concept to working … more
    Google (12/20/25)
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  • Lead Architect, Custom Silicon

    Global Foundries (Richardson, TX)
    …(eg, ISO 26262, IEC 61508). Required Qualifications: + Deep experience architecting custom silicon , ASIC, or SoC designs (digital/ mixed-signal ). + Expertise in ... and project leadership skills. Preferred Qualifications: + 15+ years of experience in custom silicon , ASIC, or SoC development with a track record of leading… more
    Global Foundries (11/03/25)
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  • Sr. Full Chip Physical Design Engineer…

    SpaceX (Sunnyvale, CA)
    …will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: + Perform SOC top level physical design; floor-planning, I/O, bump & ... Sr. Full Chip Physical Design Engineer ( Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded...SKILLS AND EXPERIENCE: + Experience and deep understanding of SOC top level physical design… more
    SpaceX (12/15/25)
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  • Lead Post- Silicon Validation Engineer

    NVIDIA (Santa Clara, CA)
    …and working with memory systems in the lab. + Direct experience in taking an SOC /GPU from concept level to production. + Experience in DRAM, high speed DRAM ... We are seeking Lead Post- Silicon Validation Engineer within the GPU Engineering Team...initial power-on through production. + Ability to understand the Top N issues in a myriad of data. +… more
    NVIDIA (11/06/25)
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  • Sr. Manager - SoC Virtual Platform…

    Amazon (Cupertino, CA)
    …the servers they power. Our models are used by AWS internal teams for silicon verification and to left-shift software development (as a virtual platform). We are ... you will: * Lead the team responsible for developing SoC models end-to-end, including model architecture, integration with other...debug * Mentor and develop the team, while hiring top talent to continue scaling * Lead new product… more
    Amazon (12/17/25)
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  • ASIC/FPGA Principal SoC Engineer VI

    Lockheed Martin (Denver, CO)
    …Lockheed Martin Space's Silicon Solutions team and seeking a future\-looking Principal SoC Engineer who is able to cast and realize a compelling vision which ... **Description:** Join Our Team as an **ASIC/FPGA Principal SoC Engineer** where you will work on the...you must be a US Citizen for consideration\. **Clearance Level :** Top Secret **Other Important Information You… more
    Lockheed Martin (12/18/25)
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  • Sr. ASIC Design Engineer ( Silicon

    SpaceX (Irvine, CA)
    …Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design ... Sr. ASIC Design Engineer ( Silicon Engineering) Irvine, CA Apply SpaceX was founded...problems including clock domain crossings and power optimization + ASIC/ SoC system integration experience + Experience with multicore CPU… more
    SpaceX (12/19/25)
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  • Chip Architect - ARM-based SoC Design…

    Broadcom (San Jose, CA)
    …and memory. + ARM-based SoC Architecture: Define and drive the top - level architecture for complex SoCs utilizing various ARM processor cores (Cortex-M, ... This role is central to bridging the gap between system requirements and silicon implementation, with a strong focus on mixed-signal integration for sensing and… more
    Broadcom (11/25/25)
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  • Senior Product Manager, Tensor SoC

    Google (San Diego, CA)
    …Requirement Documents (PRDs). + Collaborate with Pixel and Android partners to identify top use cases and metrics driving silicon requirements. + Partner with ... Senior Product Manager, Tensor SoC _corporate_fare_ Google _place_ Mountain View, CA, USA;...+ benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is… more
    Google (12/13/25)
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  • Principal Physical Design Engineer

    Microsoft Corporation (Hillsboro, OR)
    …**Principal Physical Design Engineer** to join the team. **Responsibilities** + Responsible for SOC Top Level Design Planning and partitioning strategies. + ... **Overview** Microsoft Silicon , Cloud Hardware, and Infrastructure Engineering (SCHIE) is...on or leading projects from beginning-to-end. + Experience in SOC Top Level work, Design… more
    Microsoft Corporation (12/19/25)
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  • Hardware Engineer

    Cisco (San Jose, CA)
    silicon failure analysis (FA) on ATE and CFT to replicate and diagnose system- level failures, applying silicon debug tools to isolate issues. + Collaborate ... along with 5+ years' experience in IC test engineering, SOC /VLSI test bring-up, characterization and production testing. + Strong...experience in silicon test debug, root causing silicon failures to flop or cell level .… more
    Cisco (12/18/25)
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  • Senior ASIC Design Engineer - Clocks IP

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top -notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... efficient clock programming sequence. The team works with the silicon solution team to triage silicon or...we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. + Get… more
    NVIDIA (10/28/25)
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  • Sr Principal Product Engineer - Memory IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …related to memory protocols such as DDR, LPDDR, HBM, and GDDR, and to engage with top technology companies making an impact in our world. We are seeking a Post ... Silicon Memory Product Engineer to support silicon ...and debug of Memory IP subsystems. + Support customer SOC and system integration, including ATE deployment and production… more
    Cadence Design Systems, Inc. (11/22/25)
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  • Senior ASIC Design Engineer, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …buses like AMBA AXI4 - Experience in integrating third party IP blocks, building top level modules, defining clock domains and power domains - Knowledge of ... various DSP ISA - Experience in entire design flow from architecture to final silicon . - Experience debugging system- level issues - Good programming skills in… more
    Amazon (12/12/25)
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  • ASIC/FPGA Principal Verification Engineer VI

    Lockheed Martin (Highlands Ranch, CO)
    …security clearance, you must be a US Citizen for consideration\. **Clearance Level :** Top Secret **Other Important Information You Should Know** **Expression ... this role look like?** We are building the best SOC team in the world at Lockheed Martin Space's... team in the world at Lockheed Martin Space's Silicon Solutions team and seeking a future\-looking Principal Verification… more
    Lockheed Martin (12/06/25)
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  • Signal Processing Associate Engineering Manager

    Lockheed Martin (Denver, CO)
    …security clearance, you must be a US Citizen for consideration\. **Clearance Level :** Top Secret **Other Important Information You Should Know** **Expression ... **Description:** The Silicon Solutions team of Lockheed Martin Space is building the best SOC team in the world and are seeking a highly talented and… more
    Lockheed Martin (12/06/25)
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  • ASIC Engineer, Formal Verification

    Meta (Raleigh, NC)
    …and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level 3. Work with Architecture and ... close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level 5. Build reusable/scalable environments for Formal Verification and… more
    Meta (12/20/25)
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  • Principal Customer Platform Architect / Systems…

    Advanced Micro Devices, Inc (Austin, TX)
    …where you draw from a broad spectrum of technical experience including silicon , platform hardware, and software to deliver sophisticated products. THE PERSON: As ... system and/or chip development, you work across swim lanes and guide system- level server technical execution. KEY RESPONSIBILITIES: In this role you will utilize… more
    Advanced Micro Devices, Inc (12/08/25)
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  • Senior Accelerated Computing Product Manager

    NVIDIA (Santa Clara, CA)
    …from you! From compiler flags and kernel configurations to energy efficiency and SoC features, this is an outstanding role that touches on deeply technical facets ... deployment but allows for the opportunity to advise significant outcomes "at the top of the stack" via incisive analysis of data and concise communication.… more
    NVIDIA (11/22/25)
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  • ASIC Design Engineer, Cloud-Scale Machine Learning…

    Amazon (Austin, TX)
    …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... services. Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us...technical field - 5+ years in RTL design for SOC - 5+ years in VLSI engineering - 5+… more
    Amazon (12/16/25)
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