- Google (Sunnyvale, CA)
- …AXI) and scripting languages (ie Tcl, Python or Perl). + Experience in UPF for low-power design , including power intent specification, verification, and ... this role, you will join a team working on SoC -level RTL design for our data center...data paths. + Develop and maintain Unified Power Format ( UPF ) specifications for power management of the design… more
- SpaceX (Irvine, CA)
- Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER ...and STA Signoff. + Experience with power intent and upf development for block and soc top.… more
- Meta (Austin, TX)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more
- Meta (Austin, TX)
- …execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power and higher performance trade-offs. 4. ... Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design … more
- Capgemini (Santa Clara, CA)
- **Job Title:** ** Design Verification Engineer ** **Job Location: Santa Clara CA** **Job description:** *Architect and Create verification environments using ... design engineers. * Create low power testcases using UPF or CPF to verify the desired power intent...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification Engineer_ **Location:** _CA-Santa… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from ... development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... of complex digital top level and/or blocks, with experience across the complete ASIC/ SOC design flow including routing, static timing closure, EM/IR analysis and… more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... of enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects… more
- Microsoft Corporation (Raleigh, NC)
- …of Artificial Intelligence and Computing. We are looking for a **Senior Silicon Engineer ** to join our team! If you are like tackling complex Register Transfer ... methodology for large and intricate digital System on Chip ( SoC ), this is the perfect place for you! You...is responsible for developing and delivering the latest Electronic Design Automation (EDA) technologies to various silicon teams within… more
- Fresh Consulting (Redmond, WA)
- …in RTL coding, synthesis and/or SoC Integration. - Experience in digital design uArchitecture. - Experience with UPF -based simulation flow. - System Verilog ... - Support hand-off and integration of blocks into larger SOC environments. - Assist with Algorithm analysis, verification and...minimum) - 4+ years of experience as a Digital Design Engineer and/or a Chip Lead. -… more
- Meta (Sunnyvale, CA)
- **Summary:** We are currently seeking a machine learning performance modeling engineer to support the development of a custom machine learning software/hardware ... software and SoCs for AR/VR devices. **Required Skills:** Performance Modeling Engineer Responsibilities: 1. Lead power and performance modeling of IP components… more
- Meta (Sunnyvale, CA)
- …Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer ... Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and...and PrimeTime-STA for the blocks and the top-level including SOC . Analyze the inter-block timing and come up with… more
- Qualcomm (San Diego, CA)
- …to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, verify, ... validate, implement, and document IP (block/ SoC ) development for a variety of high performance, high...power intent + Manage timing constraints + Trouble shoot upf issues in synthesis + Run Conformal Low Power… more
- Qualcomm (San Diego, CA)
- …high performance ASIC/ SoC design flows (micro-architecture, RTL design , verification, synthesis, timing/STA, UPF , CLP, LEC formal verification, DFT, ... and, ability to execute critical power analysis of critical design IPs for path to DDR. This is a...This is a great opportunity to join a fast-paced SoC team responsible for development of next Generation, high… more