- SpaceX (Irvine, CA)
- Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING ...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $170,000.00 - $230,000.00/per year Your actual level and… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... to make this possible, with the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Amazon (Austin, TX)
- …discipline, or equivalent experience * Experience in developing and managing complex SOC ASIC solutions including embedded processors and memory with high-speed ... manage the Austin Design Center responsible for defining, implementation ( SOC / RTL / IP), and bring-up of Project...systems being developed in house on top of the ASIC solutions built by this team. Job responsibilities In… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering) at... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- Teradyne (North Reading, MA)
- …delivers better business results. Opportunity Overview Teradyne is seeking a Senior Principal Semiconductor Product Definer in the Silicon Strategy and Technology ... IP's roadmap and continual development in response to long-term market trends. T his senior role features extensive senior management exposure, and is a leading… more
- Qualcomm (San Diego, CA)
- …entering new area such as the PC market. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. Besides ASIC and/or FPGA ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and methodology...As new projects are coming up, making it wonderful timing to join our team. An ideal candidate will… more
- Amazon (San Diego, CA)
- …advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC ... latest generation of Echo devices is looking for a Sr . SOC Design Engineer-STA to continue to...STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. - Full chip timing constraints development,… more
- Amazon (San Diego, CA)
- …role you will: . Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets. . Define, ... configure and integration SoC Subsystems . Contribute to the SoC ...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's ... leading SoC 's and GPU's. This position offers you a unique...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- Capgemini (San Francisco, CA)
- …digital top level and/or blocks, with experience across the complete ASIC / SOC design flow including routing, static timing closure, EM/IR analysis and ... **Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development,… more
- NVIDIA (WA)
- We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- NVIDIA (Santa Clara, CA)
- …the clocks design. + Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to improve ... today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...The Team is responsible for crafting all aspects of SOC clocking. The team collaborates with the front end… more
- US Tech Solutions (San Jose, CA)
- …ASIC design on several production tape-outs. * Experience in Designing RTL block for an SOC . * Experience in integrating ASIC IP into an SOC . * Experience ... portions of the design and implementation of blocks to meet functional, timing , area, and power requirements. * Collaborate with architecture and hardware teams… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC 's and GPU's. This position offers the opportunity to have ... to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/ timing clean design. + Support post-silicon validation activities. + Work with… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... fully verified design by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure… more
- Qualcomm (San Jose, CA)
- …help create a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer, you will define, model, design, optimize, verify, validate, implement, and ... document IP (block/ SoC ) development for a variety of high performance, high...Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.… more
- NVIDIA (Santa Clara, CA)
- …+ Together with other team members, we deliver clock information to GPU, CPU and SOC verification team, timing and DFT teams. You will use Perl to improve ... today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
- Qualcomm (Santa Clara, CA)
- …to volume chip production for at least one product cycle is preferred Keywords: ASIC ; SOC ; Low Power; Power estimates; Power Intent; Power Implementation; WiFi ... Technology team you will be working on WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/Implementation, power estimates and power… more