- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (Goleta, CA)
- …scripting) - must be able to automate test or regression flows **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... engineer who can work independently and take ownership of verification deliverables within a UVM / SystemVerilog ...tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC). + Strong… more
- NVIDIA (Austin, TX)
- …design verification experience + Experience in pre-silicon verification ( UVM , SystemVerilog ), ASIC design /implementation flow, and design ... components using SV/ UVM methodology + Driving coverage-based verification closure + Collaborate with design teams...the crowd: + Previous experience automating tasks in the design verification process + Hands on experience… more
- Data Device Corporation (Bohemia, NY)
- …inVHDL;working knowledge ofVerilog, SystemVerilog and UVM for function verification . + FPGA Design Tools: Proficiency in Xilinx Vivado required; ... involves developing robust testbenches, creating advanced simulation environments, executing verification suites, and collaborating closely with Design Engineers… more
- Actalent (Wayne, NJ)
- …JOB SKILLS & QUALIFICATIONS: + ACTIVE SECRET CLEARANCE + Experience with FPGA design verification + Proficiency in SystemVerilog and Verilog + Knowledge ... **NEW FPGA DESIGN VERIFICATION ENGINEERING OPPORTUNITY SUPPORTING A...and coverage closure. The code will be developed using SystemVerilog /Universal Verification Methodology (SV/ UVM ) following… more
- Meta (Austin, TX)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Micron Technology, Inc. (Minneapolis, MN)
- …strong foundation in ASIC verification . **Responsibilities** + Work with UVM -based SystemVerilog testbenches to verify ASIC functionality. + Collaborate with ... learn, communicate and advance faster than ever. **Department Introduction** Micron's ASIC Design Verification team ensures the functionality and quality of… more
- Capgemini (Seattle, WA)
- …Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in design ... **Job Description:** We are seeking a SoC Design Verification Engineer to join our...+ 8 to 10 years of hands-on experience with SystemVerilog and UVM methodology. + Proficiency in… more
- Northrop Grumman (Jessup, MD)
- …The Systems Engineering Integration & Test (SEIT) department is seeking a Staff Lead Design Verification Engineer to join our team and develop these technologies ... verification processes. **Role And Responsibilities:** The Debug and Staff Lead Design Verification Engineer will be responsible leading the verification … more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven … more
- Teradyne (North Reading, MA)
- …logic verification using SystemVerilog & Universal Verification Methodology ( UVM ) + Experience in logic design writing RTL in Verilog HDL + ... experience + Knowledgeable in digital logic verification , preferably using SystemVerilog & Universal Verification Methodology ( UVM ) + Familiarity… more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- BAE Systems (Nashua, NH)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- Snap Inc. (Vancouver, WA)
- …AR + Work closely with digital design , analog logic, software and verification engineers + Develop and implement UVM -based and assertion-based testbenches + ... learning, and working better together. We're looking for a Design Verification Engineer to join the Spectacles...automation Knowledge, Skills & Abilities: + Strong knowledge of UVM and SystemVerilog for advanced verification… more
- Northrop Grumman (Jessup, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting...with Polygraph. + Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience Northrop… more
- Meta (Sunnyvale, CA)
- …test cases using industry-standard verification languages and methodologies (eg 4. SystemVerilog , UVM ). 5. Perform simulation and debugging of ASIC designs ... 2. Collaborate with design engineers to understand design intent and identify potential verification challenges....languages (eg Verilog) and verification languages (eg SystemVerilog ) with in UVM (Universal Verification… more
- Capgemini (Santa Clara, CA)
- …and Implement Solutions** Design and deploy **end-to-end SoC verification environments** leveraging UVM , UPF, and advanced methodologies. **Engineer ... accelerate delivery. **Your Profile** + **15 years** in SoC design / verification with expertise in UVM ,...UVM , UPF, and protocol VIPs. + Proficiency in ** SystemVerilog ** , **VHDL** , and scripting languages (Python, TCL).… more
- Renesas (Morrisville, NC)
- Associate Design Verification Engineer Job Description Renesas is looking for a talents to join our team as a Electrical Engineer ( Design Verification ) ... test coverage, efficiency, and overall + effectiveness of the verification process. + Debug and report design ...power electronics. + Proficient with simulation environments using Verilog, SystemVerilog , UVM , Python, Perl etc. + Experience… more