- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- BAE Systems (Nashua, NH)
- …generating scripts (Perl, Tcl, Python, shell, etc.) + Working knowledge of UVM / SystemVerilog and familiarity with design verification + Working knowledge ... has an open position for a Principle FPGA Digital Design Engineer! See what you re missing. Our employees...+ Experience with designer-level test bench (VHDL, Verilog, or SystemVerilog ) + Familiarity with revision control (GIT, CVS, Clearcase,… more
- BAE Systems (Austin, TX)
- … team + Experience with high speed ADC/DAC interfaces + Experience with UVM / SystemVerilog and working with design verification teams + Working knowledge ... Description** BAE Systems is seeking a Senior Principal FPGA Design Engineer! See what you re missing. Our employees...Engineering Group is looking for a Senior Principal FPGA Design Engineer to support FPGA designs through all phases… more
- Actalent (Grand Rapids, MI)
- … verification methodologies and networking technologies. Essential Skills + Proficiency in UVM , SystemVerilog , and FPGA design tools (eg, Vivado, ... ) Job Description We are seeking a skilled FPGA UVM Verification Engineer with a strong experience...identify and resolve issues. + Work closely with FPGA design engineers to understand design specifications and… more
- Skyworks (Cedar Rapids, IA)
- …Skills + BS & 5+ yrs (MS & 3+ yrs) experience in integrated circuit design / verification required + Expert in SystemVerilog and HDL programming languages + ... will include but not be limited to creating generalized SystemVerilog UVM testbenches with full functionality coverage...new verification tools to be used by verification / design teams + Work with design… more
- Google (Madison, WI)
- …RTL using SystemVerilog for ASICs. Preferred qualifications: + Experience with verification methodology (eg, UVM /OVM/VMM). + Experience with the full ... and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer, you will use your...+ Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology ( UVM… more
- Meta (Austin, TX)
- …in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience with Design verification of ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...development cycles 9. 14+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Austin, TX)
- …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more
- Meta (Austin, TX)
- …based verification . 9. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Track ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Austin, TX)
- … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs,...15. Experience in development of UVM based verification environments from scratch. 16. Experience with Design… more
- Meta (Austin, TX)
- …UVM methodology. 10. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... 9. 3+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and ...14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design… more
- Meta (Sunnyvale, CA)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more
- Qualcomm (Santa Clara, CA)
- …PCIe controller, Coherent Interconnects, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage ... is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology... SystemVerilog + 5+ years of experience with verification methodologies such as UVM or OVM… more
- Qualcomm (San Diego, CA)
- …planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage development, ... related field + 2+ years of experience with ASIC design and verification tools, techniques, and methodology...and methodology + 3+ years of experience with digital design concepts and RTL languages such as SystemVerilog… more
- Northrop Grumman (Linthicum, MD)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl,… more
- Amazon (Boise, ID)
- …working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. ... What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will...CS. - 7+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and UVM… more
- Google (Madison, WI)
- … scenarios. + Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology ( UVM ). + Identify ... degree or PhD in Electrical Engineering. + 6 years of experience in design verification . + Experience with industry-standard simulators, revision control systems… more
- Northrop Grumman (Annapolis Junction, MD)
- …Systems Engineering Integration & Test (SEIT) department is seeking a **Staff Lead Design Verification Engineer** to join our team and develop these technologies ... verification processes. **Role and Responsibilities:** The Debug and **Staff Lead Design Verification Engineer** will be responsible leading the … more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more