• ASIC Rtl Design

    Broadcom (San Jose, CA)
    …We are seeking for an experienced RTL Designer for our team. The engineer will be responsible for design & development of digital circuits including defining ... experience is a plus. + Experience in micro-architecture and RTL development. + Worked on architecture definitions on clocks,...in Tcl, Perl, Python scripting + Good understanding of ASIC design flow + Strong interpersonal skills… more
    Broadcom (11/01/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …Bachelor's Degree in EE, CE, or other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC verification using ... and review of code and functional coverage. * Ensure RTL quality with qualifying the design with...design in emulation. * Oversee and manage the ASIC bring-up process. Who You Are The Core Hardware… more
    Cisco (10/01/24)
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  • ASIC Digital Design Engineer

    Qualcomm (San Jose, CA)
    …a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design , optimize, verify, validate, implement, and document ... Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related...power use, and verification or similarly for custom circuit design /layout flow. * Utilizes tools/applications (eg, RTL more
    Qualcomm (09/23/24)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …the lab. Who You'll Work With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... * Bachelor's degree in Electrical or Computer engineering. * 4+ years of ASIC Design experience. * Excellent Verilog/System Verilog programming skills. *… more
    Cisco (11/08/24)
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  • ASIC Design for Test Engineer

    Cisco (San Jose, CA)
    ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design ... integration with the testability features coordinated in the RTL . * Work closely with the design / design -verification and PD teams to enable the integration… more
    Cisco (11/01/24)
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  • ASIC Engineer

    Cisco (San Jose, CA)
    …/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification ... for ASIC bring up Minimum Qualifications * 8+ years ASIC design verification experience with Bachelor's or Master's degree in equivalent experience. *… more
    Cisco (10/01/24)
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  • ASIC Engineer II (Intern) United…

    Cisco (San Jose, CA)
    …understanding of engineering fundamentals and technical problem-solving skills * Familiarity with ASIC design flow, including RTL (Register Transfer Level) ... Knowledge of EDA (Electronic Design Automation) tools used in the ASIC design process is also beneficial. Why Cisco #WeAreCisco, where each person is unique,… more
    Cisco (09/14/24)
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  • Senior Staff Engineer , Electrical…

    Renesas (San Jose, CA)
    Senior Staff Engineer , Electrical Design Job Description +...synthesized, and post route netlists + Fluent in Verilog RTL coding and ASIC design ... Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal...communications skills + 8+ years of direct experience in ASIC /IC design with deep knowledge of whole… more
    Renesas (11/09/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design ... activities. What You'll Do You will be part of ASIC physical design Team which is responsible...which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer more
    Cisco (10/23/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    …some of the most complex ASICs being developed. Your Impact As a physical design engineer you will be spearheading the implementation of complex multi-hierarchy ... design of an end-to-end IP or integration of ASIC /SoC design . * Design custom...Area). * Experience and knowledge of hardware architecture and RTL /logic design for timing closure, specifically experience… more
    Cisco (11/05/24)
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  • Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …to their limits. This particular position requires the individual to be part of ASIC Design effort of the next generation emulation processors Job Requirements: ... years of related experience; or Master's + Experience in RTL development of complex ASIC /SoC. + Comfortable...the development of complex logic systems. + Aware of ASIC design flow. Experience with design more
    Cadence Design Systems, Inc. (09/19/24)
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  • Design Verification (DV) Engineer

    Cisco (San Jose, CA)
    …being developed in the industry. What You'll Do You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of ... Who You'll Work With You will work with front-end RTL Design and Verification teams and Architects...work with SDK and Software teams as part of ASIC development to create a flawless handshake between hardware… more
    Cisco (10/30/24)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    … specifications from the marketing requirements and/or system requirements + prepare detailed design document, timing constraint file + RTL coding, Lint checks, ... RTL simulation and synthesis. + In-depth knowledge for design for low power and design for...manufacturing. + Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or… more
    Broadcom (11/01/24)
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  • Senior Principal Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …innovators who want to make an impact on the world of technology. Senior Principal Design Engineer - Systems and Interfaces San Jose Job Description: The Cadence ... (CSG) develops and licenses IP designs for SoC and ASIC systems. This includes high-performance DSPs, CPUs, Interface IP,...CSG Central Applications Engineering team seeks an experienced SoC design engineer to integrate and support Cadence… more
    Cadence Design Systems, Inc. (10/08/24)
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  • Senior DFT Engineer

    Cisco (San Jose, CA)
    ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design ... including memory BIST and boundary scan. * Prior experience with hardware design specifications and verification plan/matrix, RTL & testbench implementations. *… more
    Cisco (10/17/24)
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