- Cisco (Maynard, MA)
- …to a company culture that empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Technical Lead Engineer will be working on ... or equivalent related work experience. . Experience with the latest ASIC verification methodologies, tools, and scripting/programming languages . Experience… more
- Microsoft Corporation (Santa Clara, CA)
- …tests, debugging failures and coverage signoff. Leads application of random-stimulus, coverage, formal verification , or other verification techniques to find ... projects, including cluster/subsystem and fullchip environments. + Ability to lead large scale verification execution, driving multiple senior level… more
- Northrop Grumman (Jessup, MD)
- …in Verilog, System Verilog or VHDL RTL + Circuit synthesis, formal verification , and static timing using state-of-the-art digital ASIC design tools + ... test plans. Must be knowledgeable in synthesis, SDC constraints, formal verification , and static timing. Knowledge of...or eligibility + Experience with chip level integration and ASIC chip lead - Strong design automation… more
- Amazon (Hawthorne, CA)
- …-Master's or Ph.D degree in Electrical / Communications Engineering -Exposure to Formal verification -Experience with physical implementation flows Amazon is an ... Lint (RTL, DFT, UPF), Power Analysis and STA -Take the lead and work with verification teams to define functional coverage -Work with pre-silicon verification… more
- Huntington Ingalls Industries (Fort Meade, MD)
- …of FPGA and ASIC designs. Candidates for this position will help lead teams of digital designers to utilize industry-standard functional verification tools ... https://vimeo.com/732533072 Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies is seeking out-of-the-box thinkers… more
- Cisco (Milpitas, CA)
- …in the full FPGA development lifecycle, including independent RTL coding, verification , high-speed design practices, and debugging on hardware. The Intermediate ... achieve timing closure for major functional blocks within the FPGA. + Verification : Develop and enhance functional testbenches, verification components, and… more