- US Tech Solutions (Goleta, CA)
- …independently and take ownership of verification deliverables within a UVM /SystemVerilog environment. + The engineer will collaborate with design, ... **Job Description:** + The Verification Engineer will contribute to the... prior to tape-out. **Responsibilities:** + Perform pre-silicon functional verification of digital designs using UVM and… more
- Meta (Sunnyvale, CA)
- …build IP and System On Chip ( SoC ) for data center applications. As a Design Verification Engineer , you will be part of an agile team working with the best in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , SoC Verification Responsibilities: 1. Define and… more
- SpaceX (Irvine, CA)
- SOC Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. SOC DESIGN VERIFICATION ENGINEER (SILICON...in electrical engineering or computer engineering + Experience with verification methodologies such as UVM + Strong… more
- Global Foundries (Richardson, TX)
- …information, visit www.gf.com. Summary of Role: Seeking a Senior System-on-Chip Design Verification engineer to verify the High-Performance Data Processing Unit ... or related field + 5-8 years of experience in SoC verification . + Expertise in writing.... + Expertise in writing tests using SystemVerilog , UVM and C . + Experience with scripting languages… more
- Amazon (Austin, TX)
- …- BS Degree or Higher in EE or CS or CE. - 8+ years of design verification experience using System Verilog and UVM - 8+ YOE in testbench development including: ... levels of design including: custom blocks, IP blocks, sub-systems, and fullchip SOC system testing. - Experience using multiple verification platforms. -… more
- Lockheed Martin (Denver, CO)
- …total system cost and schedule\. * Partner with a Principal Verification Engineer to architect cohesive approaches to SoC development that reduce cost and ... **Description:** Join Our Team as an **ASIC/FPGA Principal SoC Engineer ** where you will work...**Desired Skills:** * Experience in modern ASIC/FPGA/ SoC verification strategies as appropriate, including UVM /SystemVerilog, emulation,… more
- Meta (Menlo Park, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a agile team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- … to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a team working with the best in the ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies… more
- Meta (Sunnyvale, CA)
- …build IP and System On Chip ( SoC ) for data center applications. As a Design Verification Engineer , you will be part of an agile team working with the best in ... silicon success. **Required Skills:** ASIC Engineer , Performance & Package Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- …architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement IP/ SoC verification ... of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience in EDA tools and scripting… more
- Lockheed Martin (Highlands Ranch, CO)
- …for complex SoC 's and multiple chip designs leveraging multiple verification strategies as appropriate, including UVM /SystemVerilog, emulation, formal ... **Description:** Join Our Team as a **ASIC/FPGA Verification Engineer ** where you will work...verification of FPGA and ASIC devices utilizing modern verification methodologies such as UVM \. * Experience… more
- Microsoft Corporation (Mountain View, CA)
- …manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join our team! **Responsibilities** + Perform pre-silicon ... verification for complex IP, including creating testplans, developing Universal Verification Methodology ( UVM ) components and environments from scratch,… more
- Meta (Sunnyvale, CA)
- … 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience in EDA ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement … more
- Broadcom (San Jose, CA)
- …verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM ); designing verification ... flows and DV methodologies + Strong working knowledge of object oriented verification languages (OVM, UVM , etc.), C/C++, Perl, and scripting skills. +… more
- Northrop Grumman (Linthicum Heights, MD)
- …of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. + ... you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification ...+ 3 years of experience with FPGA or ASIC verification using UVM + Experience developing testplans,… more
- Microsoft Corporation (Mountain View, CA)
- …related to Microsoft cloud hardware. We are looking for a Senior Design Verification Engineer for customer focused solutions, insight and industry knowledge to ... Cloud infrastructure. We are looking for a Senior Design Verification Engineer to join the team. **Responsibilities**...base other complex IP/blocks or subsystems. + Experience with IP/ SOC verification for a full product cycle… more
- BAE Systems (Westminster, CO)
- …may be available based on position level and/or job specifics. **Senior Principal FPGA Verification Engineer - $15K Sign On Bonus** **115210BR** EEO Career Site ... of concept, and production programs. + Verify FPGA designs (including SOC architectures utilizing soft-core processors, digital filters, image processing algorithms,… more
- NVIDIA (Austin, TX)
- …The NVIDIA System-On-Chip ( SOC ) group is looking for an experienced ASIC Verification Engineer ! In this position you will have the chance to create ... focus will be on verifying and improving the related verification methodologies for the corresponding design (RTL). For this... at multiple environment levels (eg, unit, sub-system, and SOC ). What you'll be doing: + Design and maintain… more
- NVIDIA (Austin, TX)
- …The NVIDIA System-On-Chip ( SOC ) group is looking for an entry level ASIC Verification Engineer ! In this position you will have the chance to create a ... focus will be on verifying and improving the related verification methodologies for the corresponding design (RTL). For this... at multiple environment levels (eg, unit, sub-system, and SOC ). What you'll be doing: + Design and maintain… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Join us today! We are now looking for a Senior System Verification Engineer to join our Emulation division and will be working onsite ... Knowledge of CPU - GPU coherency + Experience with UVM verification environments and scripting with Perl,...+ Be familiar with hierarchical design approach, top-down design, SoC and system level verification . + Zebu… more