• Sr. Full Chip Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
    SpaceX (01/11/26)
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  • Senior C++ Software Engineer - Chip

    NVIDIA (Santa Clara, CA)
    engineer , you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll be Doing: + Work as ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level… more
    NVIDIA (01/10/26)
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  • Design Engineer - Chip

    Broadcom (Fort Collins, CO)
    …exceeding 1 GHz, from concept through production. **Role Overview** This Floorplanning Engineer role focuses on chip -level physical architecture and integration ... before you apply.** **Job Description:** Be part of the Custom Silicon Design Team within Broadcom's ASIC Products Division in beautiful Fort Collins, Colorado.… more
    Broadcom (11/12/25)
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  • Principal SoC Design Verification…

    Global Foundries (Richardson, TX)
    …markets. For more information, visit www.gf.com. Summary of Role: Seeking a Senior System-on- Chip Design Verification engineer to verify the High-Performance ... is a leading full-service semiconductor foundry providing a unique combination of design , development, and fabrication services to some of the world's most inspired… more
    Global Foundries (12/12/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are looking to hire a Chip Design Verification Engineer to join NVIDIA Chip Design group. The work environment is versatile, educational, dynamic ... AI data centers. We are seeking a senior verification engineer to help us ensure the quality and correctness...you will be doing: + Work in a combined design and verification team which develops core units within… more
    NVIDIA (01/10/26)
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  • SoC Physical Design Engineer

    Google (Sunnyvale, CA)
    …TPU architecture and its integration within AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer , you will collaborate with ... SoC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale,...(RTL), Design for Testing (DFT), Floorplan, and full- chip Sign off teams. Additionally, you will solve technical… more
    Google (01/13/26)
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  • Chip Integration Engineer

    Broadcom (San Jose, CA)
    …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The ... limited to the following: 1). Defining in the microarchitecture and implementing design of chip top level modules for L2/L3 Network Switching and routing ASICs… more
    Broadcom (11/19/25)
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  • Chip Power Integrity Engineer

    Broadcom (Fort Collins, CO)
    …**Job Description:** **You will fit this role if:** + You are an expert in full- chip power integrity analysis using state of the art tools that are able to parallel ... level through PDN simulations **More specifically we are looking for a chip power integrity expert with the following hands-on know-how:** + Developed innovative… more
    Broadcom (11/06/25)
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  • Chip Architect

    Texas Instruments (Dallas, TX)
    We are seeking a talented ** Chip Architect** to join our ACS team which develops cutting edge ASSP ICs. This individual will play a key role in **architecting ... mixed-signal chips** , **partitioning digital and analog design blocks** to optimize functionality and performance, especially for **high-speed clock and data… more
    Texas Instruments (11/07/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Austin, TX)
    Join the NVIDIA System-On- Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering ... or other industry-standard scripting languages + Experience in RTL design (Verilog), verification (SystemVerilog), System-On- Chip design /implementation… more
    NVIDIA (01/10/26)
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  • ASIC Hardware Design Engineer - New…

    NVIDIA (Austin, TX)
    …impact on the world. Join the NVIDIA System-On- Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies ... engineers. + Learn and run RTL checks to ensure design quality (eg, cross clock domains (CDC), clocks, reset,...clock domains (CDC), clocks, reset, latency, and more). + Design and implement RTL features (microarchitecture and RTL) with… more
    NVIDIA (12/10/25)
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  • Princ Engineer Design Enablement…

    Global Foundries (Malta, NY)
    …as a manager:* Perform in-house chip development to aid in understanding the customers design / technology * Design chip elements to get electrical data ... + Perform in-house chip development to aid in understanding the customers design / technology + Design chip elements to get electrical data out of the … more
    Global Foundries (12/20/25)
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  • Package Design Engineer

    Google (Sunnyvale, CA)
    Package Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more junior team ... package design . + Experience in working with cross-functional teams including chip design , SI/PI, and PCB design teams. + Experience in physical… more
    Google (12/20/25)
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  • Principal/Senior Principal Electromechanical…

    Northrop Grumman (Baltimore, MD)
    …career. Northrop Grumman Mission Systems is seeking a Principal/Senior Principal Electromechanical Design Engineer to join our team of qualified, diverse ... This position may be filled as a Principal Electromechanical Design Engineer or a Senior Principal Electromechanical...clearance is required to start + Experience with PWB/CCA design and signal routing, including chip -scale packaging… more
    Northrop Grumman (12/24/25)
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  • CPU Design Methodology Engineer

    NVIDIA (Hillsboro, OR)
    We are now looking for a CPU Design Methodology Engineer ! The complexity of chip development has greatly increased over the years. We are now packing tens of ... ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build...or equivalent experience + 5+ years of experience in chip design , specializing in SOC integration and… more
    NVIDIA (01/10/26)
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  • Principal/ Senior Principal Digital ASIC Circuit…

    Northrop Grumman (Jessup, MD)
    …deliver remarkable new advantages to the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom digital ... listed below:** **Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:** + Bachelor's degree in...Experience with chip level integration and ASIC chip lead - Strong design automation skills… more
    Northrop Grumman (12/05/25)
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  • Product Design Engineer , PhD,…

    Google (Sunnyvale, CA)
    Product Design Engineer , PhD, University Graduate, Platforms Infrastructure _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving ... and contributing to research and project planning. From the chip to chiller, you will be responsible for designing...and help facilitate training and development. As a Product Design Engineer , you will design more
    Google (01/13/26)
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  • ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    …to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of a team working with the best ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure... Verification Responsibilities: 1. Define and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to… more
    Meta (12/20/25)
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  • Signal and Power Integrity Engineer , PhD,…

    Google (Sunnyvale, CA)
    …AI/ML-driven systems. As a Signal Integrity/Power Integrity Engineer , you will lead chip and package design , ensuring optimal Signal Integrity (SI) and Power ... Signal and Power Integrity Engineer , PhD, University Graduate _corporate_fare_ Google _place_ Sunnyvale,...production. You will collaborate within a cross-functional team, including chip design , Intellectual Property (IP), system … more
    Google (12/16/25)
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  • Digital Design Engineer

    Meta (Austin, TX)
    **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a industry-leading group of researchers and engineers, and use your digital ... ICs to drive our industry leading wearable systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level… more
    Meta (01/10/26)
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