- Meta (Austin, TX)
- A leading technology firm in California is looking for an ASIC Formal Verification Engineer. This role involves leading formal verification efforts ... with various cross-functional teams. Candidates should have extensive experience in design verification and formal verification methodologies, along with… more
- SQL Pager LLC (Sunnyvale, CA)
- …and flows * Hand-on experience: System Verilog, C++, Perl/Python, UVM, Synthesis, Formal Verification , Static Timing Analysis * Experience with processor design, ... computing architecture * Participating in Architecture definition and modeling, verification test plan and testbench. * Developing the micro-architecture...years or PhD with 8+ years, 5+ years in ASIC design team lead . * Experience in… more
- Intel Corporation (Santa Clara, CA)
- …junior engineers. Candidates should have a Bachelor's degree and extensive experience in ASIC verification , particularly in formal methods. This hybrid ... A leading semiconductor company is seeking a Senior Formal Verification Engineer for AI SoC development in California. This role involves shaping verification… more
- Murata Manufacturing Co., Ltd. (San Diego, CA)
- …Strong understanding of design verification techniques such as UVM and formal verification methods Experience in IP development and integration Understanding ... in Chennai, India. The Technical Director is expected to lead , hire, train, and mentor engineers to develop industry‑leading...RF and AMS circuits for ASIC /Module level verification … more
- Apple Inc. (Sunnyvale, CA)
- …ASICs with track record of successful silicon tapeouts. Deep knowledge of ASIC verification flows with SystemVerilog and UVM including testbench architecture, ... scenarios and environmental conditions throughout Apple's product ecosystem. Responsibilities Lead subsystem-level verification of Radio digital controllers /… more
- Analog Group (San Jose, CA)
- …test benches and automated test cases. Responsible for synthesis, timing closure, and formal verification . Create scripting to support design and verification ... flow and tools knowledge. Candidate will be expected to lead designer, verification , and be technical focus...target schedule. Qualifications: 3-5 years' experience in design plus verification of ASIC or FPGA. Strong knowledge… more
- Medium (San Jose, CA)
- …architectures. Partition designs and justify tradeoffs across HW/FW/SW; collaborate with ASIC /SoC, digital design, verification , board, and systems teams. Bring ... light-and redefining what's possible in the optical age. Job Description Lead architecture and development of firmware across multi‑processor embedded subsystems… more
- Altera (San Jose, CA)
- …including RTL development, synthesis, linting, clock-domain crossing (CDC) checks, and formal verification .* Collaborate across teams (design, CAD, and ... and signoff (DRC/LVS).* Frontend design flows (RTL development, synthesis, linting, CDC, formal verification ).* Scripting and automation using Python, Tcl, and… more
- Intel Corporation (Santa Clara, CA)
- …while ensuring design integrity for physical implementation. Working closely with verification teams, you'll review verification plans and implementation to ... quality assurance compliance for smooth IP/SoC handoff.**Key Responsibilities** * Lead evaluation of architectural trade-offs considering features, performance targets,… more
- Apple Inc. (Cupertino, CA)
- …Engineering Program Manager, you'll drive critical silicon development schedules and lead technical issue resolution for test chips that validate our next-generation ... design team. Interface and drive issues within multi-functional teams: Design, Verification , DFT, Validation, Technology, Digital IP, Analog IP, Physical Design.… more
- Cisco (Maynard, MA)
- …to a company culture that empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Technical Lead Engineer will be working on ... or equivalent related work experience. . Experience with the latest ASIC verification methodologies, tools, and scripting/programming languages . Experience… more
- Microsoft Corporation (Santa Clara, CA)
- …tests, debugging failures and coverage signoff. Leads application of random-stimulus, coverage, formal verification , or other verification techniques to find ... projects, including cluster/subsystem and fullchip environments. + Ability to lead large scale verification execution, driving multiple senior level… more
- Northrop Grumman (Jessup, MD)
- …in Verilog, System Verilog or VHDL RTL + Circuit synthesis, formal verification , and static timing using state-of-the-art digital ASIC design tools + ... test plans. Must be knowledgeable in synthesis, SDC constraints, formal verification , and static timing. Knowledge of...or eligibility + Experience with chip level integration and ASIC chip lead - Strong design automation… more
- Amazon (Hawthorne, CA)
- …-Master's or Ph.D degree in Electrical / Communications Engineering -Exposure to Formal verification -Experience with physical implementation flows Amazon is an ... Lint (RTL, DFT, UPF), Power Analysis and STA -Take the lead and work with verification teams to define functional coverage -Work with pre-silicon verification… more
- Huntington Ingalls Industries (Fort Meade, MD)
- …of FPGA and ASIC designs. Candidates for this position will help lead teams of digital designers to utilize industry-standard functional verification tools ... https://vimeo.com/732533072 Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies is seeking out-of-the-box thinkers… more
- Cisco (Milpitas, CA)
- …in the full FPGA development lifecycle, including independent RTL coding, verification , high-speed design practices, and debugging on hardware. The Intermediate ... achieve timing closure for major functional blocks within the FPGA. + Verification : Develop and enhance functional testbenches, verification components, and… more
